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80 Kudos
--thatguy

Logic Operators and Arrays

Status: Completed Submitted by Member on 06-30-2010 11:33 PM 4 Comment

It would be nice to be able to use logic operators on arrays in Single Cycle Timed Loops.

  17863i0D7A4F514670B8AB

61 Kudos
Intaris

Change the font in the Xilinx Log window to fixed width

Status: Completed Submitted by Proven Zealot Proven Zealot on 07-24-2014 07:42 AM 3 Comment

Xilinx log window should use a fixed-width font.

 

Which of these two string indicators with identical content is easier to read?

 

FPGA Xilinx Log font.png

 

Spoiler
The one on the left is Courier, the one on the right is the default Application font
10 Kudos
hsinhsiang

Find FPGA Register

Status: Completed Submitted by Member on 08-05-2016 11:31 AM 12 Comment

I hope the FPGA Register Function Could Add "Find Caller"....

 

1.png

 

2.png

10 Kudos
--thatguy

Scale by Power of 2 and Fixed Points

Status: Completed Submitted by Member on 07-01-2010 07:38 AM 2 Comment

With LVFPGA I work almost exclusively with fixed point numbers, and having to convert my numbers to 8 bits or 16 bits just to use the scale by power of 2 function isn't convienient.

 

17949iDCF3B4A5081C518C

4 Kudos
MarcoMauri

Multiple Compile Servers

Status: Completed Submitted by Active Participant on 05-14-2010 02:35 AM 2 Comment

I would suggest to implement the possibility to use at the same time multiple compile servers.

Imagine you have a project with many FPGA targets: it would be useful to send the FPGA vis to compilers working in paraller (a sort of Compiler Farm....).

 

Cheers,

Marco

 

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2 Kudos
Harlequinade

Minimize FPGA Compile server to icon

Status: Completed Submitted by Member on 05-06-2010 08:03 AM 2 Comment

Having two computers, one for developing and one desktop pc for administrative work, I use the desktop as compile server for compiling the FPGA VIs. The compilation takes about 45 minutes, during which I can't develop anything in LabVIEW. By sending the data to the desktop pc, I can resume my work. Though on the desktop machine it's annoying to always leave this program open and get closed accidentally from time to time or I forget to start it in the morning after booting the pc.

 

Suggestions:

- Minimize the LabVIEW FPGA Compile Server to system icon tray

- Option for starting the Compile Server on booting of the OS. 

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1 Kudos
gsussman

Prompt the user when an FPGA compile has completed

Status: Completed Submitted by Active Participant on 11-19-2010 01:13 PM 1 Comment

I know that when connected to the compile server the local compile status window will show you when a compile is done, however that does seem to severely limit productivity in that the only way you can get back to working in LV is to disconnect from the compile server. The downside is that you don't get any feedback as to when your compile has completed. This is especially true if your compile server is running on a remote machine.

 

Why not add a feature to LabVIEW to allow disconnecting from the compile server but still provide a background polling feature to update the user when the compile has completed. Something as simple as a dialog box telling me that my compile is ready would be great. It would allow me to get back to work on other sections of the code while still closing the loop on the running FPGA compile process and alerting me that it is done.

 

If the system polled once every minute or so that would be more than adequate.