Home > Community > Discussion Forums

LabVIEW FPGA Idea Exchange

Showing results for 
Search instead for 
Do you mean 
The NI Idea Exchange is a product feedback forum where NI R&D and users work together to submit ideas, collaborate on their development, and vote for the ones they like best. View all of the NI Idea Exchanges to post an idea or add your opinion on an existing one today!
New Idea
0 Kudos

run-time selection of FPGA resources

Status: New
by Trusted Enthusiast on ‎04-08-2016 02:01 PM

I would like to select which FPGA resources (DMA FIFOs, front-panel controls) are used by a host VI at run-time. This would make it possible to implement multiple copies of the same function on an FPGA and control them with the same driver, passing in a reference to the appropriate resources. For example, my FPGA might be communicating with several identical devices over SPI. I'd like to write one host/real-time driver, and then pass in a reference to which front-panel controls to use for that particular device.


It seems like NI has already done some work in that direction, with the FPGA Advanced Session Resources (appears to be LabVIEW 2014 only) and Software Defined Instruments (only on a limited set of boards). I'm looking for a simple interface that's available on all FPGA targets.

0 Kudos

When an RMC is added in the project, the I/O is organized automatically in folders:


This is not the case when using an RMC Socket after creating a custom CLIP:


It would be really helpful if folders could be created to organize the I/O for an RMC Socket. 


0 Kudos

Optimized Error-Case with error-code separated cases (see LabVIEW Idea Exchange)

Status: New
by Member BAT_BU ‎03-18-2016 08:31 AM - edited ‎03-18-2016 08:38 AM

Sorry, I post this into the wrong forum.


See my idea/suggestion in "LabVIEW Idea Exchange".

I would like to have a feature to access several IO pin ranges to avoid programming this for a 9205 cRIO module:


With DIO modules like NI9403 you can program this:


Why not provide Mod2/AI0:31 in the above image? (With subranges like AI0:7, AI8:15,… similar to DIO module?)


When you compile on your own machine, the output of the "coregen" step is cached and used on subsequent compiles.  This saves considerable time.  The fact that this does not happen on the NI cloud service erases any speed gains (and more).


You could:

 - Cache cores at NI.  Save for xx days since last use (or forever if space is not an issue)

 - Transfer cores when they exist (cached locally) to compile server along with other intermediate files


FIFO read that doesn't use 100% CPU

Status: New
by Member igagne on ‎07-16-2015 01:21 PM

The FIFO read looks like an event based node (like a dequeue or wait on occurance) and I think there's a lot of people that assume it's going to use minimal cpu resources while it is waiting for data. I'm wondering if we can have an option that behaved like that. For example, could we have fixed sized FIFO read where the FPGA could trigger an interupt to let the RT side know the data is ready?

0 Kudos

I love the FPGA Desktop Execution Node. I'd love it even more if I could access global variables from the FPGA VI that is being emulated:


Globals in DEN.png


I normally use globals as opposted to controls and indicators to curve FPGA resource usage in cases where I won't need those values available through the FPGA Interface on the deployed application.

0 Kudos

Relative Paths for Xilinx IP

Status: New
by Member AndyBrown on ‎06-10-2015 02:06 PM

When using the Xilinx IP nodes in LabVIEW FPGA it becomes very difficult to support source code control and branching.  The biggest issue is the fact that the "Folder for Support Files" entry is absolute.  So when we need to branch the code to isolate new feature development from the main trunk the relative path is now wrong.  Please make this and all other paths relative to support a more robust development environment.



0 Kudos


Status: New
by Member Opuk on ‎06-03-2015 09:10 PM

Dear All,

I am extremely new to Labview and programming for that matter but I want to start learning labview for my research and i am hopeful with this forum to learn more and more. I want to write a graphical program to perform a raster scan as an initial step in my project. Could someone kindly assist me on this. Thank you.


Kind Regards,


This is the current situation when dealing with register creation on FPGA targets:


Regsiter Create.png


This is what I would like:


Regsiter Create wishful thinking.png


I am currently creating a group of classes to abstract out inter-loop communication and the ONLY thing changing between classes (aside from variations between Ragister vs FIFO vs Global and so on) is the datatype.  Being able to link the Register creation to a data input (the data value of the class itself for example) would save a lot of work in such operations.  If it were also possible to do the same for the Register stored within the class private data then implementing different classes int his way would be really easy.


Even without classes, the ability to autoadapt the type of registers / FIFOs in this way would be a real step towards re-usable code on FPGA.



0 Kudos

erreur lors de la compilation de l'FPGA

Status: New
by Member CrisSTine01 on ‎04-15-2015 05:52 AM


Voici l'erreur que j'obtiens quand je veux compiler mon programme FPGA



LabVIEW FPGA: La compilation a échoué à cause d'une erreur Xilinx.

ERRORSmiley Tongueack:2310 - Too many comps of type "SLICE" found to fit this device.

Design Summary:
Number of errors: 1
Number of warnings: 89
Logic Utilization:
Number of Slice Flip Flops: 7,963 out of 10,240 77%
Number of 4 input LUTs: 10,607 out of 10,240 103% (OVERMAPPED)
Logic Distribution:
Number of occupied Slices: 5,523 out of 5,120 107% (OVERMAPPED)
Number of Slices containing only related logic: 4,143 out of 5,523 75%
Number of Slices containing unrelated logic: 1,380 out of 5,523 24%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 11,028 out of 10,240 107% (OVERMAPPED)
Number used as logic: 10,454
Number used as a route-thru: 421
Number used as 16x1 RAMs: 70
Number used as Shift registers: 83
Number of bonded IOBs: 90 out of 324 27%
IOB Flip Flops: 97
Number of MULT18X18s: 38 out of 40 95%
Number of BUFGMUXs: 2 out of 16 12%

Peak Memory Usage: 359 MB
Total REAL time to MAP completion: 19 secs
Total CPU time to MAP completion: 19 


voici une capture ecran du programme 

merci d'avance Smiley Happy

Improvements for Continuous Integration

Status: New
by Member AndyBrown on ‎02-25-2015 09:48 AM

Proper unit testing is a key component of large LVFPGA project success.  As the number of modules grows, so does the number of units tests increase.  We are working on automatic continuous integration methods that will continue to monitor the accuracy of all modules and assemblies throughout the project life cycle.  IP Integration node and NI's wrapper around Xilinx IP makes this task more difficult.  When our continuous integration machine refreshes the source code from the repository it has to regenerate these nodes in order to compile.  The "Regenerate IP Integration Node Support Files..." tool does not always properly update all IP.  It seems like the NI wrappers around Xilinx IP are most problematic.  The only way a computer can properly update its version of the node is to open the VI and click through the Xilinx IP generation pages to get it to update.


As a rule we do not commit build products into our source code repository.  One option would be to submit all the support files generated when first creating the IP integration node so that others users might not have to update.  This can become messy and quickly unwielding.  The problem arrises when changes to the IP integration node cause more or fewer support files to be generated.  This then requires deleting some files from the repository and adding others which is tedious and leads to errors.  One compromise would be if the IP integration created one single compact file that contains all the information needed (expect the input vhd, etc. files) that could be committed to the repository.  Even better would be to roll this information into the VI itself.  Neither of these might be ideal if the support file contents take up a lot of disk space.


Regardless there needs to be a better solution to allow for automated continuous integration testing.

Improve Compile Retrieval Process

Status: New
by Member AndyBrown on ‎02-25-2015 07:34 AM

Long compile times are a necessary evil of FPGA code.  Even with the vast improvements of Vivado, compile time still ranks as the biggest killer of large project efficiency.  As compile times approach 3-4 hours, their successful completion becomes paramount.  All too often I find that the Xilinx compiler running on the compile worker has completed successfully however some small communication glitch either between my development machine and the farmer or the farmer and the worker has caused the compile to be lost.  It is quite frustrating to know you have a completed bitfile from Xilinx but the NI tools will not perform the final processing steps required to create the lvbitx file.  The only solution is to restart the compile costing another 3-4 hours of productivity.


Typical workflow in our company for these large projects is to spend mornings testing and stressing the compile(s) from overnight.  Then make any bug fixes and incremental feature improvements and try to start a compile by mid-morning.  By mid-afternoon when the compile is complete do the process again so that you can process another build for overnight.  If one of the compiles fails because of timing or resource problems, there's nothing that can be done.  But if it fails because of glitches in NI's compile wrapper code, that becomes a waste of a half of a day of productivity.


I propose that the current methods for compiling bitfiles be modified.  The goal is to improve user productivity.  Some of my suggestions include:

  • For a given build specification, give it the ability to re-attempt to retrieve the last completed compile. This option would be available even if the VI's that created that compile had been modified.
  • If a compile was completed previously for this build specification and there has yet to be a successful lvbitx generation, prompt the user before doing anything that would destroy the ability to retrieve it.
  • Make sure that all of this still works when changing connections to the worker.  For example if I start my compile at work then take my laptop home and want to login to my VPN at night to check on my compile
  • Don't remove any chance to get a compile if there was a communication error.  Right now when I get the communication error, I see a red X in the compilation status and my only option is to remove it from the list.

Better FPGA FP Control Selection

Status: New
by Trusted Enthusiast Trusted Enthusiast on ‎01-13-2015 10:36 AM

When there are many controls on the front panel of the FPGA, selecting the control from a Read/Write Control node in the host can become a pain.  It is one very large list of controls on the front panel of the FPGA.  This list has no scrollbar, no browse, or search feature, and no obvious way of grouping controls.


Here is one example of a front panel, and a video showing how long it takes to scroll through the list of contorls.


FPGA Front Panel.png


And here is the video of me scrolling through the controls:  http://screencast.com/t/PLzptTwq58aw


There is plenty of room for improvement.  Here are just a few ways I think NI could make this better.


Browse and Search


When using a Property Node, or Invoke Node, the very top option is to "Browse..."  From here a list of all properties, or methods can be seen in a resizeable window.  Here you can also search, and sort alphabetically.  The Read/Write Control node could have similar functionality making selection of controls easier.


Front Panel Selection From FPGA


There could be an option for creating a node by selecting the controls on the front panel of the FPGA.  A solution that may work today, is to select the controls, then invoke a custom QuickDrop command that creates the node and puts it in the clipboard so it can be pasted in the host VI.  If this were to become an option, I'd hope there is a way to combine two nodes into one, by concatenating the controls of one onto the other. 


Front Panel Selection From Host


Lets say you already have the Read/Write Control node on the host.  There could be an option by right clicking that would open a new window, showing a static image of the front panel of the FPGA, which the user could then click on.  This would be great because the developer probably already knows the control they want based on the front panel location.  I don't know how possible this is because you could load a bit file which won't have any front panel information. 


Easier Grouping of Controls


Right now there is a way to group controls of an FPGA.  This feature is never talked about, and doesn't work on dynamic bit files.  Here is a discussion where I describe the steps to make controls grouped on the host.  Still this isn't supported on all FPGA setups, and you have to conform to a specific naming convention.  Why can't controls that are grouped on the front panel, just be grouped in the host?



This idea exchange is really for any kind of improvement to the FPGA control selection.

Get reference to currently deployed bitfile on FPGA target

Status: New
by Active Participant smithd on ‎11-13-2014 11:15 AM - last edited on ‎02-25-2015 10:31 AM by Active Participant Dragis

Basically I want a VI like open FPGA VI ref which takes a RIO interface and returns a reference, except that it doesn't deploy a reference if one doesn't exist. It would instead pop out a boolean or error if you try to get a reference and there is no bitfile already deployed.


Two use cases I have in mind:


-Imagine if you need a cRIO to start working ASAP so you deploy your bitfile to flash and tell it to run on power-up. You still have to package the exact same bitfile with your RTEXE, even though its already deployed. This increases the size of your RTexe significantly. Lets say you version your RTexe and don't version the FPGA deployed to flash. Depending on what the signature check is, obtaining a reference to your bitfile may cause the "new" bitfile to be redeployed, eliminating the advantage of loading your bitfile onto flash in the first place.


-Imagine if you have a framework like veristand where you need to use a single bitfile in multiple locations which were written by different developers and possibly released at different times. The tools on NI labs (https://decibel.ni.com/content/docs/DOC-35574) help a lot and let you, once you have a reference, confirm the reference has all the interfaces you need to run your code. However, if you need to share references between code modules you must still be sure to obtain it in just one place and then share the reference yourself using a global or FGV.


Having the RIO driver solve this would be very helpful.

Hi How about facility of import and export of I/O Label in FPGA-Real time project as shown image instead of manually renaming each I/O


IO Label.jpg

0 Kudos

FlexRIO Breakout Extender

Status: New
by Active Participant xl600 on ‎10-24-2014 05:13 PM

There needs to be a way to physically probe the FlexRIO card edge when a NI or custom module is installed.  A time honored method of debugging has always been to probe signals with an o-scope or logic analyzer.  To route debugging signals to unused pins (EX: Within a CLIP) for probing seems a necessity when dealing with hardware and FPGAs.


Lets get them to design one and make it into a purchasable accessory!

0 Kudos

This has been a huge frustration in my development.  There is no way to debug a Flex RIO + NI1483 FPGA design other than to tweak, compile, and test with actual hardware.  NI should provide a VHDL behavioral simuation of all of their modules so that full end-to-end simulation can be performed using advanced simulators such as ModelSim.  This would facilitate a much more robust FPGA development cycle for their customers who have these types of tools available.


For the NI1483, a VHDL simulation combined with a VHDL Camera Link behavioral model would be even better.  But the CameraLink model could be developed by the customers as it (At least) is a standard or can be gleened from camera manufacturer documentation.

I've searched but can't see anything similar - please add a method for setting the timeout for FPGA nodes. This includes the 'Open FPGA reference' and FPGA IO nodes.


If you disconnect a cRIO FPGA (e.g. NI 9148) from the network, it takes 20-30s for the IO node or Open FPGA reference to execute. This is really bad for the user experience as if they try to exit their application in this time it may take half a minute for the application to exit. It also means you may have to wait that length of time to realise that your FPGA has disconnected under most use cases (you can obviously have an external watchdog loop to check that the node is executing in a timely manner)


Please allow me to configure the timeouts for these nodes similar to the TCP/UDP or VISA nodes. They are very similar in how they operate to the FPGA nodes (i.e. a hardware device driver which is susceptible to disconnects!) so I don't understand why these have been omitted.


I wouldn't mind having to set the timeout as part of opening the FPGA reference and then internally have it use the same timeout for other IO nodes as follows:




Allow project hosted IO module CLIP

Status: Already Implemented
by Active Participant xl600 on ‎09-18-2014 12:32 PM

While attempting to debug NI1483 issues, I found it necessary to make modifications to the NI1483 CLIP.  In LabView 2014 and earlier, it's not possible to maintain your own IO Module CLIP directory.  One must maintain all IO Modules within the IO module search path (<National Instruments>\Shared\FlexRIO\IO Modules folder ).  This can be done by copying an existing IO module to a new path within the <National Instruments>\Shared\FlexRIO\IO Modules folder, then editing the *.tbc file to rename the "model" key.  The main issues with this approach are the potential lack of administrator permissions and the difficulty of maintaining source control in a non-project related system directory.


The suggestion is thus:


1. Give the user an option to select the path of the IO module under the IO module Properties General Category (When Enable IO Module is selected).


That's it!


Status: Already Implemented

You can add the modified CLIP in the FPGA target properties like you would a user-defined CLIP.  When you configure the IO module, the modified CLIP will show up along with the rest of the CLIPs.

About LabVIEW FPGA Idea Exchange

Have a LabVIEW FPGA Idea?

  1. Does your idea apply to LabVIEW in general? Get the best feedback by posting it on the original LabVIEW Idea Exchange.
  2. Browse by label or search in the LabVIEW FPGA Idea Exchange to see if your idea has previously been submitted. If your idea exists be sure to vote for the idea by giving it kudos to indicate your approval!
  3. If your idea has not been submitted click New Idea to submit a product idea to the LabVIEW FPGA Idea Exchange. Be sure to submit a separate post for each idea.
  4. Watch as the community gives your idea kudos and adds their input.
  5. As NI R&D considers the idea, they will change the idea status.
  6. Give kudos to other ideas that you would like to see in a future version of LabVIEW FPGA!
Top Kudoed Authors