LabVIEW FPGA Idea Exchange

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It would be nice to be able to use logic operators on arrays in Single Cycle Timed Loops.

  17863i0D7A4F514670B8AB

With LVFPGA I work almost exclusively with fixed point numbers, and having to convert my numbers to 8 bits or 16 bits just to use the scale by power of 2 function isn't convienient.

 

17949iDCF3B4A5081C518C

I would suggest to implement the possibility to use at the same time multiple compile servers.

Imagine you have a project with many FPGA targets: it would be useful to send the FPGA vis to compilers working in paraller (a sort of Compiler Farm....).

 

Cheers,

Marco

 

Having two computers, one for developing and one desktop pc for administrative work, I use the desktop as compile server for compiling the FPGA VIs. The compilation takes about 45 minutes, during which I can't develop anything in LabVIEW. By sending the data to the desktop pc, I can resume my work. Though on the desktop machine it's annoying to always leave this program open and get closed accidentally from time to time or I forget to start it in the morning after booting the pc.

 

Suggestions:

- Minimize the LabVIEW FPGA Compile Server to system icon tray

- Option for starting the Compile Server on booting of the OS. 

I know that when connected to the compile server the local compile status window will show you when a compile is done, however that does seem to severely limit productivity in that the only way you can get back to working in LV is to disconnect from the compile server. The downside is that you don't get any feedback as to when your compile has completed. This is especially true if your compile server is running on a remote machine.

 

Why not add a feature to LabVIEW to allow disconnecting from the compile server but still provide a background polling feature to update the user when the compile has completed. Something as simple as a dialog box telling me that my compile is ready would be great. It would allow me to get back to work on other sections of the code while still closing the loop on the running FPGA compile process and alerting me that it is done.

 

If the system polled once every minute or so that would be more than adequate.