How to optimize this labview fpga vi??

[mangood]

Hi to all

I have build  this vi that do a special operation as in figure below

I use IP node to build a counter

I face two problem 

1-the counter never count the number of one I did not why

2-how to replace the divide and mul operation  by shift operation to give best area??

I accept any suggestion

best regards 

m.s

labview fpga 2012 vi

vhdl code for counter

[nathand]

I have a couple of suggestions:

1) Stop posting so many different threads. Keep all your FPGA questions in one place; I assume somehow they're all related. Explain your overall project in clear, detailed English. Your diagrams (like the one here) are not very helpful. With regards to the diagram, for example, you show a random number generator, but there is none in your VI. What are you actually trying to do here?

2) Take a LabVIEW course. If you can't take one in person, at least work through some of the tutorials. Also, use the debugging tools that LabVIEW provides. You could replace your counter with an equivalent LabVIEW block and then run it on your computer with execution highlighting (the lightbulb icon) to see what this code does; I do not think it does what you want it to do.

3) Dividing by 8 is equivalent to a right-shift by 3. Multiplying by 4 is equivalent to a left-shift by 2.

[mangood]

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@nathand wrote:

I have a couple of suggestions:

1) Stop posting so many different threads. Keep all your FPGA questions in one place; I assume somehow they're all related. Explain your overall project in clear, detailed English. Your diagrams (like the one here) are not very helpful. With regards to the diagram, for example, you show a random number generator, but there is none in your VI. What are you actually trying to do here?

2) Take a LabVIEW course. If you can't take one in person, at least work through some of the tutorials. Also, use the debugging tools that LabVIEW provides. You could replace your counter with an equivalent LabVIEW block and then run it on your computer with execution highlighting (the lightbulb icon) to see what this code does; I do not think it does what you want it to do.

3) Dividing by 8 is equivalent to a right-shift by 3. Multiplying by 4 is equivalent to a left-shift by 2.

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First I am not a  newbie  in using Lab View
But recently I purchased Lab Vue 2012 with  FPGA module
I was faced with many problems in this release differ from the previous release, and I have the right to put my problems in this forum and share ideas with others and You do not have the right to punish me.
I've put the problems here that are not found in web pages and therefore these subjects Benefit others!!! And 3 or 4 thread will not affect on other!!!???
I have read the policy to use the service there was no requirement determines the number of threads that are put here in one day

I also remember you that we pay a lot of money to bay a labview,

 fpga module is new and their are many problem related to it

so we need to be sure that labview fpga work well to bay ni device like rio and others.

2) Take a LabVIEW course

no  ni Branch in my country

 execution highlighting (the lightbulb icon) to see what this code does; I do not think it does what you want it to do.

I do it before post hte thread and it not work I don't know what is the problem with it so come here to ask.

3) Dividing by 8 is equivalent to a right-shift by 3. Multiplying by 4 is equivalent to a left-shift by 2.

I have std_logic output so how to do this operation in right manner

 random number generator, but there is none in your VI. What are you actually trying to do here?

this is the random number with counter and available in vi 

[nathand]

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@mangood wrote:

I was faced with many problems in this release differ from the previous release, and I have the right to put my problems in this forum and share ideas with others and You do not have the right to punish me.
I've put the problems here that are not found in web pages and therefore these subjects Benefit others!!! And 3 or 4 thread will not affect on other!!!???

---

This isn't punishment; it's a suggestion that it would be easier to help you if you keep all your discussions in one place, since I assume they are related. For example in a previous thread you asked for help, several people volunteered their time to provide answers, and then you posted that none of them worked because you are using FPGA. If you kept your discussions in the same place, it would have been immediately clear that you were continuing to ask more questions about FPGA, and would not waste the time of forum contributors posting solutions that didn't help you.

[mangood]

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@nathand wrote:

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@mangood wrote:

I was faced with many problems in this release differ from the previous release, and I have the right to put my problems in this forum and share ideas with others and You do not have the right to punish me.
I've put the problems here that are not found in web pages and therefore these subjects Benefit others!!! And 3 or 4 thread will not affect on other!!!???

---

This isn't punishment; it's a suggestion that it would be easier to help you if you keep all your discussions in one place, since I assume they are related. For example in a previous thread you asked for help, several people volunteered their time to provide answers, and then you posted that none of them worked because you are using FPGA. If you kept your discussions in the same place, it would have been immediately clear that you were continuing to ask more questions about FPGA, and would not waste the time of forum contributors posting solutions that didn't help you.

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i am sorry for any wrong from me,

know this is good suggestion, ""all thing in one thread "" 

>>>>>>>>
let now back to the problem becuse our time is important 

i cant make a shift operation because i did not know where is the point""fixed ponit"" since i use std_logic_vector

the accumlator that work as conuter in  fpga module its output integer this  also  make me confuse about how shift operation will be

 

[nathand]

I'm sorry, I still do not understand what you are trying to do. I am not sure where you are using the accumulator. I am not a VHDL programmer, but I modified your VI to replace the IP block with what I believe is similar LabVIEW code as shown below and then ran it. I don't see how this is a random number generator, it always produces the same result. Why are you using fixed-point values instead of integers? Assuming the random number generator works, does it produce integers or fixed-point numbers? Where are you using the accumulator?

[mangood]

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@nathand wrote:

I'm sorry, I still do not understand what you are trying to do. I am not sure where you are using the accumulator. I am not a VHDL programmer, but I modified your VI to replace the IP block with what I believe is similar LabVIEW code as shown below and then ran it. I don't see how this is a random number generator, it always produces the same result. Why are you using fixed-point values instead of integers? Assuming the random number generator works, does it produce integers or fixed-point numbers? Where are you using the accumulator?

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Hello
Thank you for your  beautiful response.

This circuit is part of the my academic research  and do a special operation
the vi that developed by You are beautiful, but the reason that prevented me from build the same vi created by you
is that  will need  a division process  and  this very costly in terms of physical space.

This what make me put thread here

the division operation and mul in this circuit always by 2^n  where n; integer(4,8,16,32,64.....)

so all I need a shift operation to right or left,

so for the vi that developed by you, can we replace the division and mul by a shift??

or is the labview have an intelligent optimizer and will put a shift operation instead of division ???

i find a 'shift operation' in "data manupulation" in labview main menu but i suffer to get right result

 best regards

[nathand]

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@mangood wrote:

so for the vi that developed by you, can we replace the division and mul by a shift??

or is the labview have an intelligent optimizer and will put a shift operation instead of division ???

i find a 'shift operation' in "data manupulation" in labview main menu but i suffer to get right result

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Yes, you can replace the divide by 8 with a shift, IF you have appropriate fixed-point representations or if you do not mind losing bits. In order for this to work without losing any bits, you would need a fixed-point value with at least 3 fractional bits (for example if the overall width is 8 bits, you'd have 5 integer bits, leaving 3 bits for the fraction). You would then need to shift the initial set of bits to the correct locations to be an integer value - if you start with a 4-bit integer, you would need to shift it left 3 bits, then reinterpret the shifted bits as a fixed-point number.

Can you provide some specific inputs and outputs to explain what you want to achieve? For example, if the random number generates 5, what should the output be?

Alternatively, can you write a non-FPGA LabVIEW program that does what you want? We can then help convert that to something that will be efficient on an FPGA.

[mangood]

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nathand wrote:

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Can you provide some specific inputs and outputs to explain what you want to achieve? For example, if the random number generates 5, what should the output be?

Alternatively, can you write a non-FPGA LabVIEW program that does what you want? We can then help convert that to something that will be efficient on an FPGA.

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hi

thank you for enteraction with me

this  is  a simple non-FPGA LabVIEW program 

you can see the mul and divide operation 

these are only that  i have a problem with them in labview fpga

the resolution for input 14 word length and 4 bit  for integer part 

for output 14 word length and 6 bit for integer part 

best regards

m.s

[nathand]

See attached changes to your VI. This uses 32-bit fixed-point numbers (16 integer) but you can adjust as appropriate. You can also simplify further - combine the two shifts into one, and subtract the appropriate value instead of 2.