How to optimize this labview fpga vi??

[nathand]

You can only open a reference to one FPGA VI and it must be the top-level VI, not a subVI within it. For your application you need to have one top-level VI with two parallel loops, one for each function.

[mangood]

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@nathand wrote:

You can only open a reference to one FPGA VI and it must be the top-level VI, not a subVI within it. For your application you need to have one top-level VI with two parallel loops, one for each function.

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thank you for fast replay 

the top level vi  !!!

do you mean labview fpga vi??? or host vi

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[nathand]

The FPGA VI. After compiling the FPGA VI there is only a single FPGA VI - the one you compiled. It is no longer possible to get access to any subVI inside it; all the subVIs are combined into the compiled version of the top-level VI. You can only load a single compiled FPGA VI onto the FPGA at a time.

[mangood]

ok

sorry for take your time

i will make FPGA VI like this with selcetor chosse between  two loops and this will complied to FPGA
is this right >?? that what i understand from you!!!
regards

[nathand]

You do not need any sort of selector; let the two loops run in parallel on the FPGA.

[mangood]

yes its right,no relationship  among them so no need for selestor 

Oh my God, I did not think well
For this I have come to discuss with you
Oh God how I hope to work with you, but God forbid that my country very far

regards

for last

for host vi

i will do vi like this 

but how to measure  each stage delay???i try tick count but not shift reg at each stage

and for open refernce FPGa will be inside or outside  the main loop???

best regards

m.s

[nathand]

You need to open the FPGA VI Reference only once, so you should do it outside the loop.

The standard way to do timing is to add frames of the sequence structure that contain only the Tick Count function. At the end you can subtract the tick counts between frames to determine the amount of time that passed. For example see here: http://forums.ni.com/t5/LabVIEW/Can-I-increase-the-execution-speed-of-this-VI/m-p/2339808#M732173

However, running the vision acquisition in parallel with the sequence structure will affect the timing. I'm not sure why the sequence structure is necessary in your image, nor where the vision acquisition is used since there are no inputs and outputs.

[mangood]

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@nathand wrote:

You need to open the FPGA VI Reference only once, so you should do it outside the loop.

The standard way to do timing is to add frames of the sequence structure that contain only the Tick Count function. At the end you can subtract the tick counts between frames to determine the amount of time that passed. For example see here: http://forums.ni.com/t5/LabVIEW/Can-I-increase-the-execution-speed-of-this-VI/m-p/2339808#M732173

However, running the vision acquisition in parallel with the sequence structure will affect the timing. I'm not sure why the sequence structure is necessary in your image, nor where the vision acquisition is used since there are no inputs and outputs.

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dear nathand:
I done calculate delay as in figure as I understand from you

now the vision problem :let take simple example to expalin what is need

let assume that I want to make  ADC value as trigger to acquire an image so the camera must alleyway  run and only take image when the trig=1

I put the aquision  vi inside loop but in this vi  I will need FIFO

any suggestion for  best aquision position

regards:

[nathand]

You can't do it the way you show in the image. The main outer loop will not repeat until the inner vision acquisition loop ends, which is not what you want. Why do you need a while loop around the vision acquisition? Right now there's nothing in your code that waits for the trigger condition, so I'm not sure what you are trying to do.

When the trigger condition occurs, do you want to process the last image that you acquired, or the next image that you acquire?

[mangood]

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@nathand wrote:

You can't do it the way you show in the image. The main outer loop will not repeat until the inner vision acquisition loop ends, which is not what you want. Why do you need a while loop around the vision acquisition? Right now there's nothing in your code that waits for the trigger condition, so I'm not sure what you are trying to do.

When the trigger condition occurs, do you want to process the last image that you acquired, or the next image that you acquire?

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Dear
I now is wrong but I am really afraid about the best place for acquisition vi position

I want to process the image that have been acquired after the trig=1

 I mean  exactly the trig happen first then image  must acquired  after trig=1 then process image then send some value to fpga

this the sequence of operation

the kuds all to you this is simple what i can do for you

below the vi

best regards