How to optimize this labview fpga vi??

[nathand]

Try this instead, it's even simpler. It reinterprets the sum as a fixed-point number with 7 fractional bits (13-6 = 7) and then subtracts 128 (2*2^6). Same result, with no shifting, multiplication or division required at all. I currently have the output set as a 32-bit fixed-point with 25 integer bits, but you can adjust as necessary. However, if you limit it to 6 integer bits, you are likely to overflow. If you know that the end result will always fit in a 14,6 fixed-point, convert to that type at the end.

[nid28392]

Hello

I am building a digital down converter in LabVIEW. I am not able to figure out if my output is correct ( Inphase and Quadrature components). Am I on the right path? Please find attached the VI I have been working on.

Thank you.

[GerdW]

@nid,

you have now entered three different threads to post your totally unrelated question. Why don't you open your own thread?

[mangood]

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@nathand wrote:

Try this instead, it's even simpler. It reinterprets the sum as a fixed-point number with 7 fractional bits (13-6 = 7) and then subtracts 128 (2*2^6). Same result, with no shifting, multiplication or division required at all. I currently have the output set as a 32-bit fixed-point with 25 integer bits, but you can adjust as necessary. However, if you limit it to 6 integer bits, you are likely to overflow. If you know that the end result will always fit in a 14,6 fixed-point, convert to that type at the end.

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Hello nathand
I apologize for the delay in responding, but a car bomb exploded close to the Internet access provider, bringing the Internet Poor
Today returned
I thank you for simplifying my system
You really intelligent person
I'm not going to forget this work never
God bless you

also ,i will keep this thread open du to my group in unversity hear about labview fpga and they ask my many question and if i face hard question i will put it here.

best reagrds 

m.s

[mangood]

hi guys..

how can we calculate delay or number of clock in labview fpga for one excution ???

 i have this labview fpga vi for example

best regards

m.s

[nathand]

If you use Single-Cycle Timed Loops, then you can determine exactly how many clock cycles your code will take to execute without compiling. Otherwise you'll need to add some timing functions to your code to measure it, then compile and run your code. However, adding the timing functions could add additional delay. The best thing to do is to write your code to use single-cycle timed loops.

[mangood]

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@nathand wrote:

If you use Single-Cycle Timed Loops, then you can determine exactly how many clock cycles your code will take to execute without compiling. Otherwise you'll need to add some timing functions to your code to measure it, then compile and run your code. However, adding the timing functions could add additional delay. The best thing to do is to write your code to use single-cycle timed loops.

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dear nathand:

i understand from single_cycle timed loops that most of code inside it will excute in one clock with clock pirod equal to clock source that hava be connect to single cylce loop

 is this true ???

for second method do you have simple example to determin delay

 "adding the timing functions could add additional delay"

 is this mean that we will never could caculate delay extaclly!!!

best regards

m.s 

[nathand]

You do not need to explicitly connect a clock source to the single-cycle loop; it will use the FPGA clock. ALL (not most) of the code inside will execute in a single cycle. You can put a state machine inside the single-cycle loop for calculations that require more than one loop cycle. The first state will do one part of the calculation, the second state will do the next step, etc.

If you add timing functions you can still know the delay exactly - just leave the timing functions in the final code. I don't know that the timing functions will add additional delay, but it is possible. The Tick Count function can be configured to count clock cycles, so you would need to use a sequence structure with a tick count function in the first and last frames to measure the number of clock cycles needed for a particular computation.

[mangood]

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@nathand wrote:

You do not need to explicitly connect a clock source to the single-cycle loop; it will use the FPGA clock. ALL (not most) of the code inside will execute in a single cycle. You can put a state machine inside the single-cycle loop for calculations that require more than one loop cycle. The first state will do one part of the calculation, the second state will do the next step, etc.

If you add timing functions you can still know the delay exactly - just leave the timing functions in the final code. I don't know that the timing functions will add additional delay, but it is possible. The Tick Count function can be configured to count clock cycles, so you would need to use a sequence structure with a tick count function in the first and last frames to measure the number of clock cycles needed for a particular computation.

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OK THANK YOU
I WILL TRY

BEST REGARDS

M.S

[mangood]

Hi every one

today i suffer from a single problem I face it in my lab which as follow

and I need your opinion

I want to read a signal from analogue to digital converter of Spartan 3E using labview FPGA VI then enter  these value to  labview  host vi

then I do some  vision processing then  I send two value to  second labview FPGA VI   then and back again read from ADC and so on....

I have  problem or not a  problem exactly..

The ADC LV FPGA VI AND THE SECOND LV FPGA VI WILL  BE IN SAME  LABVIEW FPGA VI AND CALLED THEM USING SINGLE "OPEN FPGA VI REFERENCE" OR EACH HAVE ONE ??????

Below is my simple  vi each stage with it title

the second problem is I want to make camera always work and only processing the image acquired only after read from adc

sorry for long words

best regards

ms