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FPGA read write not taking boolean array as input

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read write control.png

I am trying to write a boolean array from the host computer to the fpga vi.. I have added the array in the fpga vi and i am trying to invoke the same using the read/write function in the host vi file...however the boolean array is not visible in the controls .. Hoever boolean variables that i added are seen in the controls...is boolean array addition not possible ?

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Hi Anupama,

 


@Anupama07 wrote:

I am trying to write a boolean array from the host computer to the fpga vi.. I have added the array in the fpga vi and i am trying to invoke the same using the read/write function in the host vi file...however the boolean array is not visible in the controls .. Hoever boolean variables that i added are seen in the controls...is boolean array addition not possible ?


Did you recompile the FPGA VI?

Did you select the correct FPGA VI/bitfile in the FPGAOpenReference function?

 

We could help much better when you would attach real code instead of an image of a small part of your code base…

 

Why is there a coercion dot at the comparison node? Yesterday you should have learned how to convert your string correctly into a boolean array!

Which target should your VI run on? Does that target have access to the (user-local) Desktop folder of your host computer?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Hi GerdW,

Yes I recompiled the FPGA VI before running the host VI. And the host VI has access to the input file i am trying to read. I was able to read the file contents in the host VI..I have attached the codes for your reference ( untitled 1.vi is the FPGA vi  and Red WriteControlUI is the host VI). I am able to get the control of the Boolean and numeric variables in the host VI but the Boolean array is not displayed..

 

Thanks

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Hi Anupama,

 

please downconvert to LV2019. And don't forget to include the lvproj file in your attachment…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Hi, 

I hope I have done the down conversion correctly. I am not able to attach the project files here. There is some error in uploading the files. 

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Hi Anupama,

 


@Anupama07 wrote:

I am not able to attach the project files here. There is some error in uploading the files. 


  1. You can ALWAYS put several files or even a whole folder of file into a ZIP file.
  2. You can attach ZIP files here in the forum…

Without the project file we cannot examine FPGA VI and their host VIs correctly!

 

Btw.: please DON'T maximize windows to fullscreen (frontpanel and blockdiagram) - that's annoying. And cleanup your VIs (AutoCleanup) for both frontpanel and blockdiagram…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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I have attached the zipped files. Hope this is ok. Thanks 

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Hi Anupama,

 


@Anupama07 wrote:

Hope this is ok.


I wrote "ZIP" two times, but you use a proprietary packer tool that is not (natively) supported by most OS.

Why do you want us to install 3rd party software just to look at your code?

Next time please use ZIP when asked for...

 

(I can open your RAR archive as I use 7z by default.)

 

And you also need to downconvert the lvproj file as it also keeps the LabVIEW version in it...

You forgot to answer my question on the used hardware (aka "target")!

 

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Hi, 

The target is PCIe-7841R ( R series FPGA ) FPGA.. And I had down converted the whole project for the 2019 version. I am not sure what mistake I made. 

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Message 9 of 12
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Hi Anupama,

 


@Anupama07 wrote:

And I had down converted the whole project for the 2019 version. I am not sure what mistake I made. 


The project file in your RAR still is for LV2021SP1, so you forgot to downconvert it…

 

To convert a whole project:

  1. Open the project in LabVIEW.
  2. Select "File->Save for previous".
  3. Select a new folder to save the downconverted project. It will include all project items automatically…
Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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