NI VeriStand ships with default I/O personalities for a variety of FPGAs. In order to create a custom I/O personality, it’s necessary to start with one of the templates that have the framework already laid out. This document contains an installation for additional NI VeriStand FPGA Support. It installs the NI VeriStand FPGA Clock Support library discussed within the Timing Engine section in Creating FPGA-Based I/O Personalities for NI VeriStand above as well as an NI VeriStand RIO Library and NI VeriStand Custom FPGA Project Wizard discussed below. Before continuing, please install the NI VeriStand FPGA Support installer.
To begin creating a custom I/O personality, first run the NI VeriStand Custom FPGA Project Wizard. The Project Wizard is accessible from LabVIEW 2012+'s create project dialog under templates (Figure 1). In LabVIEW 2011 and earlier find it in, LabVIEW’s Getting Started window (Figure 2) under Targets. You can always find it by selecting File>>New… and choosing NI VeriStand Custom FPGA Project (Figure 3).
Figure 1. LabVIEW 2012+ Project Template
Figure 2. Getting Started Window in LabVIEW 2011 and earlier
Figure 3. New File Selection in LabVIEW
The NI VeriStand Custom FPGA Project Wizard guides one through the process of selecting the FPGA and any C-Series modules that may be contained within a cRIO or C-Series Exapansion Chassis. It operates similar to the wizard for starting a new LabVIEW FPGA Project except that it adds the necessary components to the project for a custom FPGA to be used with NI VeriStand. The project wizard adds a framework template, DMA FIFOs, and corresponding XML file to begin development. It also saves the project and files to a location specified by the user. A typical project created from the NI VeriStand Custom FPGA Project Wizard is shown in Figure 4.
Figure 4. Project created by NI VeriStand Custom FPGA Project Wizard
The project wizard creates an FPGA VI in the project which is generated from a template. There are different templates for PCI, PXI, and cRIO. Both the PCI and PXI templates define the following FPGA I/O items: analog I/O on connector 0, digital lines on connector 1 acting as digital input, digital lines on connector 2 acting as digital output, and digital lines on connector 0 acting as PWM I/O. Note that if a 781xR FPGA is used, it will not have any analog I/O and will have extra digital I/O. If an R-Series Expansion Chassis is used on either connector 0 or connector 1, the digital I/O for the corresponding connector will need to be removed. The cRIO template defines I/O for NI 9215, NI 9263, NI 9411, and NI 9474 modules. The project wizard does not modify the templates according to the I/O discovered. It is the responsibility of the developer to modify the FPGA VI to match any changes in I/O from those listed above.
Figure 5. FPGA VI PXI Template
The templates are only meant to be modified by adding or removing I/O in the main frame of the communication loop and by adding or removing asynchronous loops outside of the main sequence structure. The templates have been designed so that a user should not edit anything that has a gray background or remove any of the subVIs that have a red background in the title.
The FPGA template can be customized by adding basic I/O to the communication loop. When adding inputs, convert the data to U64 packets, expand the build array, and connect the U64 packets to the build array.
Figure 6. Adding Inputs to Communication Loop
When adding outputs, first increment the “Num Packets” constant wired to the count terminal of the For loop to account for the additional packets needed by the additional outputs. Next, expand the index array function to give access to the additional packets returned by the For loop. Then connect these packets to the added outputs. If the outputs require more than one packet, build an array from the packets required and connect the array of packets to the outputs.
Figure 7. Adding Outputs to Communication Loop
When adding asynchronous loops to perform any type of processing asynchronous to VeriStand’s communication loop, create the asynchronous loop, convert any data sent to or from the loop to U64 packets, and then connect the packets between the asynchronous and communication loops via local variables. Connect the local variables in the communication loop to the DMA FIFOs by following the steps for inputs or outputs above.
Figure 8. Connecting Asynchronous Data to Communication Loop
Adding basic I/O to the communication loop and IP based I/O in asynchronous loops is made easier with the NI VeriStand RIO Library contained in the installation attached to this document.
After installing the NI VeriStand FPGA Support, NI VeriStand RIO Library will appear on the FPGA function’s palette.
Figure 9. NI VeriStand RIO Library Palette
The NI VeriStand RIO Library was created so that creating a custom FPGA bitfile for NI VeriStand will be less cumbersome and not require LabVIEW FPGA expertise. Each C-Series module with the exception of communication modules (CAN, Profibus, etc.), motion modules, removable storage modules, and third-party modules has been included in the NI VeriStand RIO Library. The modules are separated between Basic I/O and Special Case I/O.
Basic I/O consists of any C-Series module whose I/O can be placed directly in the communication loop. Customizing the FPGA VI with basic I/O only requires dropping the corresponding subVI in the communication loop, creating a constant that defines the I/O being used by the subVI, and connecting the packet input or output of the subVI to the corresponding packet receive or packet send For loop.
Figure 10. RIO Library's Basic I/O
Special Case I/O consists of C-Series modules that either use a Delta-Sigma ADC and are independently timed (such as the 9233) or consist of high resolution ADCs that execute too slow to place in the communication loop (such as the 9211). The special case I/O subVIs are meant to be placed on the block diagram as asynchronous loops. When placing the special case I/O subVI on the block diagram, its contents will be placed instead of a subVI. The contents will consist of the asynchronous loop and packet indicator. Finish by creating a local variable for the packet and placing it into the communication loop to connect to the DMA FIFO.
Figure 11. RIO Library's Special I/O
Some loops require additional processing instead of simple I/O connectivity. One example is PWM and frequency measurements. The NI VeriStand RIO Library also contains IP (Intellectual Property) Based I/O that will allow the user to quickly take advantage of the power of the FPGA with an asynchronous loop already programmed to perform a specific function. The IP Based I/O will be implemented as asynchronous loops in the same manner that Special Case I/O is implemented.
Figure 12. RIO Library's IP Based I/O
The IP Based I/O palette consists of PWM or Pulse Generation/Measurement, Encoder Input, and Quad Encoder Input. Additional IP Based I/O may be added in the future and can also be created by any user. If you create any additional IP Based I/O and wish to include it in a future release of the NI VeriStand RIO Library please comment below.
The final step to creating a custom FPGA personality for NI VeriStand is defining in XML the data sent to and from the FPGA in the 64-bit packets. Please refer to the NI VeriStand Help for the topic on Creating a Custom FPGA Configuration File.
The NI VeriStand RIO Library includes an XML snippet in each subVI that defines the data in the packets received/generated by the subVI. This snippet can be copied and pasted into the corresponding section of the *.fpgaconfig file that defines the interface from FPGA to NI VeriStand host.
If you are using multiple RIO targets (that do not have PXI timing and synchronization features like R-Series), you must take synchronization into consideration. For example, if you are using two MXIe RIO targets with a Real-Time PXI... the system performance will greatly suffer unless you synchronize the two MXIe RIO targets.
The framework provided by this add-on has built in synchronization support to accomplish this. It uses a 9401 or 9402 module to share a distributed clock between the RIO targets. This is disabled by default and must be enabled by the user. To enable this functionality:
This software is not yet officially supported by National Instruments. If you encounter a problem with these tools, or if you have suggestions for a future revision, please post to the forum for this tool: NI VeriStand FPGA-Based I/O Interface Tools Discussion. You must use this feedback forum for support. Do not call National Instruments for support for this add-on.
Fails to install in 2013, and I don't see an explanation of how to manually install the files.
I have it installed on 2013 so something must be going wrong on your machine. Are you running LabVIEW as administrator when you run the installer VI? This is required.
Also, I've noticed some people have trouble with long path names. You might want to unzip the contents (be sure to unzip before running the installer) to a short path like C:\temp
I was running as admin. The file path length was the issue. I was getting a 'generic file I/O error' prior. Now the install completed once I shortened the path.
But after I restarted LabView and I run the 'NI VeriStand FPGA Project" template I get the following error:
Unable to load FPGA Project Wizard
- LabVIEW FPGA is not installed.
- The LabVIEW FPGA installation is corrupt.
I definitely have the FPGA madule installed and it is not corrupt as I have been using it daily with no other issues.
Any help is appreciated.
Well... at least we are making some progress.
What happens if you try to start the LabVIEW FPGA Project template? (The NIVS template hooks into this one)
The LabVIEW FPGA Project template works just fine.
No, EtherCAT does not use DMA and uses a totally different interface. See the scan engine custom device page to learn how to use that with NI VeriStand: NI VeriStand Add-On - Scan Engine and EtherCAT
What if when i genereate the FPGA project for sbRio or cRio and then click on the FPGA project it asks me for FPGA PWM In/OUT and
Receive Packet From Host.vi
Send Packet to Host.vi.
How do I find these?
Whwen you are installing versinatd you need to install support for LabVIEW. As well as you need LabVIEW FPGA module installed.
The code works well and helped me a lot. Thank you!
I did have 2 issues with the QuadEncoder Position Velocity.vi:
1) the XML code snippet given in the VI block diagram uses U32 for Position, Velocity, Acceleration. This works well when the encoder is rotaing in +ve direction, but causes rollover when encoder reverses direction. I changed the XML code to I32 for Position, Velocity, Acceleration. It then worked ok.
2) If a Z-pulse (0 degree sensor) is connected, then the position is reset to 0 whenever Z-pulse is high. This is expected behavior. But the Velocity becomes a large -ve number once per revolution due to the reset of position to 0. To handle Z pulse correctly, the Velocity Calculation should be ignored when Z-pulse is high.
Hello, if I create a Custom VeriStand FPGA Project there es no syncronization/timing like in the template C:\Users\Public\Documents\National Instruments\NI VeriStand 2016\FPGA, see pictures:
Custom VeriStand FPGA:
C:\Users\Public\Documents\National Instruments\NI VeriStand 2016\FPGA\Template:
I am Efeel from china.Are you still update the toolkit?
I want to develop a HIL system with PXIe-7868R,but the Toolkit seems not support the device ,I hope you can give me some helping .
The tool does not have to support a specific FPGA. You can use a different configuration and modify it specifically for your device.
Here is an example on how to do it for the myRIO:
FPGA Configuration file to use myRIO with VeriStand .