Testbench VI

[blaza]

Hi!

I'm working with cRIO and I want to simulate sinus signal on FPGA input. I read this tutorial http://zone.ni.com/devzone/cda/tut/p/id/7445 , bud I don't understand how to simulate sinus signal on my FPGA Input.

The main problem is how to creat a Testbench VI that simulate sinus signal.

Can someone help me?

Regards

[Rodéric]

HI,

The FPGA_VI you created reads an input value every 100ms.

I guess what you are willing to do is generate a signal (use an output)

Go to palette: FPGA MathAnalysis then generation then sine wave! Configure the function (express VI) then wive the function output to the Output node!

Regards

[blaza]

I'm wanting to generate sinus signal in Testbench VI, and read him with FPGA VI.

Something like in this attachment.

Regards

[r.halas]

Hi blaza,

you can find the example in Example Finder. Just search for Custom VI for FPGA IO-Dynamically generated-RSeries.lvproj. Once you open the project, right click on FPGA target in the project tree, go to properties. In the tab Debugging you will see Execute VI on Development Computer Simulated I/O, you have to choose the right path to the VI: Custom VI for FPGA IO - Dynamically Generated.vi.

Then you can run the Read Sine Wave FPGA VI. You will see the simulated sinewave.

The example is written fro R-series card. In the case you would like to change the target for cRIO, follow this guide:

http://zone.ni.com/devzone/cda/tut/p/id/5075

I hope this helps.

Rostislav Halas

[blaza]

Hi,

First of all thanks for helpI. It works!

Do you maybe know how can we create two simulated analog outputs (two sinus signals)? In this example we have only one simulated output. I tried to copy that part of code but it doesn't work.

Regards

Blaza

[r.halas · Accepted solution]

Hi,

you just have to add one more case to the structure I/O Item Name Case Structure. Now you have just Analog In0, the I/O read function reads I/O on fpga so basically, you have to create case also for AnalogIn1 for  example, where yuo will do the same as for AnalogIn1. Context help for the VIs in the example may help you.

Try it, it should work.

Rostislav Halas

[blaza]

Ok.

Thanks!

[l3agoov]

Hello everyone, I've the same problem of Blaza but I cannot find the example in the Example Finder. I've Labview 2013.Any help?

[l3agoov]

I'm sorry,

I've to reformule the question> I've found the example but it doesn't work. My module's output is always the same value