One thing you do pick-up using the Off-The-Shelf stuff I mentioned is "Bit-stuffing".
In SDLC the data is self-clocked so the clock signal is derived from the signal line. THe clock syncronization requires regular re-syncing via a "sync-byte". SInce there is a potential that the data could be carying data that is the same as the "sync-byte" the SDLC protocl dictates that the sync-byte can never be transmitted in the data packet so "Bit-stuffing" is used where extra bits are inserted to prevent false sync-bytes.
Bit-stuffing requires manipulating the data going out and processing on the way in.
I spent some time working on fast LabVIEW code that would implement bit-stuffing. At the time I was working with 400 MHz PC. In my case I had to handle 8 channels at 2 MHz so PC's from that era simply could not keep up with all of the work for 8 ports.
So the OTS is worth concidering.
THe other bonus I picked from the Comm-Tech approach was they exposed functions that let me atack the physical layer for testing (inserting errors).
And of course there is another idea...
FPGA can be clocked at 40MHz so with the chip mentioned above, you could code up your own SDLC interface using FPGAs.
So have fun and please post back to let us know how you decide to proceed. It will help others that follow in your foot steps.
Thank you,
Ben
