Labview 2019 FPGA compilation error

[panzer099]

Hello All,

    I have encountered a problem regarding FPGA VI compilation, The plan is transfer the coding from PXI-7842R to PXI-7851R, I only created a new project with PXI-7851R target and just copying all the codes to the 7851 project. But at first there is a warning about compilation tool and finally the compilation will be abort with error. Could you please help to give some advice? Thanks a lot.

   BTW, Previously I transferred the same code from 7833R to 7842R, It is no problem over there. 7833R,7842R,7851R have same I/O configuration.

   The dev environment:LV2019 32bit;Win10 64bit; FPGA Module 32bit;Xilinx Compilation Tool for ISE 14.7.

[LucianM]

PXI-7851 seems to have a smaller FPGA (LX30) than the 7842 (LX50) with less slices, RAM and DSPs as described here so your code might not fit. If possible, attach the code and maybe members of the community will give you hints on how you can optimize your code. Also, ISE is not officially supported on Windows 10 so you can get errors because of that. I would suggest you try to compile on the cloud.

[panzer099]

Hello LucianM,
    Thanks for your reply.
    Attached the source code for your reference. Could you please help to give some suggestions to optimize the code?Thanks again!

[LucianM]

Unfortunately the latest LabVIEW version that I have is 18 so I cannot open your code. Is it possible to save it in previous version? Also it would be better if you use a zip archive instead of 7z if possible.

[panzer099]

Hello LucianM,

    Attached 18.0 version for your reference.Thanks for your help.

[LucianM]

Seems that only the files in Utilities folder were saved to version 18. The project and 7851R_18.vi are still in 19.

From the project window select File->Save for Previous Version. This should save all the files in project along with dependencies for selected version.

[panzer099]

Hi LucianM,

   Attached the new files for your reference. Thanks a lot.

[LucianM]

I got the same error as you when I compiled using cloud compile service (I don't have ISE installed) but if I reduced the number of elements of all memory blocks to 4000, compilation succeeded. Is that an option for you?

I also tried to compile using the original number of elements of 8192 and used the look-up table implementation instead of the block memory but this time I got an error related to insufficient number of LUTRAM blocks on the device.

[panzer099]

Hi LucianM,

    Many thanks for your suggestion.

    It is worth to try it, BTW, Will decreasing the number of memory blocks bring any impact with original settings? I am newbie on FPGA dev and no idea about that.

[Bathank]

Hey,

Can you pls save the project in LabVIEW 2017. May be i can give some ideas to optimize your FPGA code. Thanks!