Introducing delay before start next...

[augustg]

First and second picture shows the FPGA linked to an RT. Im trying to introduce a certain delay after "Head" is executed before Servo 1 is started. And delay again before Servo 2 started and continues to Servo 3,4,5,6, and Tail. It is a while loop until a control stop is pressed.

Question is, should the delay be put inside the FPGA or RT host?

I tried this in the picture below but failed

I need some idea on how to do it. Totally stuck right now...Thanks in advanced

[crossrulz]

How much of a delay do you want?  It seems like what you really want to do is make your FPGA code more linear, not parallel.

[augustg]

it's best if the delay is connected to a control. The delay I wanted is 1ms.

its put that way because i need to control each individual servos

[augustg]

anyone got any ideas?

[GerdW]

Hi august,

your delay is located before the FPGA property node. The node will be executed after your delay: DATAFLOW RULES!

You should have one FPGA write node to set a new "head" value, then wait, then set the "servo" values...

[augustg]

so a total of 8 different fpga's?

[GerdW]

Hi august,

when you need to set the delay in the RT host then you probably need some more FPGA write nodes (not "fpga's")...

You may program the delay in the FPGA target too...

[augustg]

so you're saying i should create another while loop with delay for controlling servo 1 parallel to the one controlling the head?

i prefer not to disturb the codes in fpga if possible

[GerdW]

Hi august,

I didn't mention any loops so far. But you can do that if you want/need them...

It all depends on the goal you want to achieve. It's up to you to reach that goal!

[crossrulz]

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@augustg wrote:

so a total of 8 different fpga's?

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No.  8 different FPGA Property nodes.  You can then put in a Wait before each one to create the delay you want.

Or, as I was saying before, create a sequence in your FPGA with the delays you want before each write to an output.