Re： Import related .vhd files(VHDL code) CLIP to Labview FPGA

[johnsnow34]

Hello,

I'm trying to import CLIP to Labview FPGA. The CLIP consists of a set of .vhd files that some are related. If I import one of the related .vhd file, labview will report the error that some related files are not compiled in library. I'v tried to first import these files reported in error, but it doesn't help. How can I solve this problem?

[johnsnow34]

If there are any missing or unclear points in the question, please feel free to ask.

[Intaris]

A CLIP is not just a VHD file.

I'm not sure your VHD code is suited as a CLIP..... Have you developed the VHD code along the guidelines provided by NI for CLIP files?

[Terry_ALE]

Will the CLIP interface to hardware?

[Intaris]

Also, I believe you need to import ALL files required for the CLIP in one go.  Essentially the entire dependency tree needs to be included AFAIK.  You seem to be trying to import only a single file..... are you sure this is all the CLIP consists of? PArt of the CLIP import is actually chekcing the syntax of the imported files (making sure all signals are routed and so on)

[T-REX$]

My $0.02 - if you're trying to import a large (more than 5-10 files) VHD heirarchy, you'll probably have much greater success with building the IP into a post synthesis netlist or DCP and then just importing that. Here's the specific steps:

• Generate synthesis files into one out-of-context DCP * in Vivado (use the local instance at "C:\NIFPGA\programs\[LabVIEWSpecificVivadoVersion]\bin\vivado.bat"
  • synth_design -top your_top_module_name -part your_full_part_name -mode out_of_context
  • write_checkpoint -force -noxdef your_top_module_name.dcp
  • write_vhd -mode funcsim your_top_module_name.vhd
• Use DCP for synthesis file and generated VHD for simulation
• Use similar steps to integrate Verilog if that's your thing

[johnsnow34]

I have tried to import all files that for this CLIP in one time. But there is also the same error. I have attached the VHD files. When it is possible, could you please see where the problem is?

And here is the error information:

[johnsnow34]

Yeah, this CLIP will interface to sbRIO 9651.

[johnsnow34]

Hello T-REX,

thanks for the reply. I think your solution is very worth trying. But I'm not very familiar with vivado. Could you please explain how to do the second step "Use DCP for synthesis file and generated VHD for simulation"?

[T-REX$ · Accepted solution]

That part is actually in LabVIEW in the CLIP configuration dialog box. The Vivado part is to run the 3 commands that I listed in my first post. This is done in the TCL Console of your Vivado project.

synth_design -top your_top_module_name -part your_full_part_name -mode out_of_context

• This command will run synthesis for the VHDL item you specify as -top in the Vivado project.
• To figure out your_full_part_name:
  • Right-click the FPGA target in your LabVIEW project and go to properties
  • append the values for type, package, then speed grade ("xc7k325tffg900-2" for the PXIe-7971 FlexRIO)

write_checkpoint -force -noxdef your_top_module_name.dcp

• This will create a post synthesis design checkpoint (DCP file) in your Vivado project's directory.

write_vhd -mode funcsim your_top_module_name.vhd

• Creates a simulation model from the top-level VHDL file you specify.

Once you have the file from steps 2 and 3, you can bring them into LabVIEW via the CLIP integration dialog. I'll reference the same image you put in your first post. Instead of selecting that vhd file, select the DCP generated by command 2, then click the set simulation behavior on the right to select the functional simulation model we generated in step 3 above.

If this isn't clear, let me know and I'll try to make some time to create a video running through this for a simple project.

Also, just for my benefit, what's your experience level with VHDL in general? Did you write this IP yourself, or find this IP online somewhere, or maybe someone else at your company wrote it?