Import related .vhd files(VHDL code) CLIP to Labview FPGA

[johnsnow34]

Hello T-REX,

you are very kind. Follow your steps, IP has been imported into the Labview.

But there is a strange problem. The ports of IP in Labview are only from one modul "AdcClock". This IP consists of several function modules. "AdcClock" is one of modules. I'm sure that I used top level file of the whole IP instead of only the file of modul "AdcClock". I will figure out where is problem.

[johnsnow34]

Hi T-REX,

this problem was solved. There is a option in Labview CLIP integration dialog - "Synthesis Module". This option defaults to "AdcClock" and it should be changed to "AdcToplevel". Now everything seems to be fine. 

This IP is a reference design created by xilinx designer. It is for serial LVDS communication with FPGA.

I asked this question in several forums, but only your solution is right. I'm very grateful for that.

[johnsnow34]

Hi T-REX,

there is still a problem with this solution. I have imported this IP into the Labview, and I can see all pins of this IP in Labview project.

But when I compiled the VI containing the pins from this IP, Labview reported error - "source file is used for simlation and not permitted to use as inputs of Labview".

Does this mean that those original .vhd files still need to import into Labview? I'v tried to import them together with files generated in your solution, but there is error same as in my first post.