I recently had a cRIO-9057 FPGA build fail due to a timing error. I'm using LabVIEW 18.02f (32 bit) and Vivado 2017.2 (64 bit).
Although the timing requirements of the 40 MHz clock I use are met, it appears some NI internal logic is failing. When I click "Investigate Timing Violations", there is one path comprised purely of non-diagram components that is failing. Most of the components of that path are prefixed with "crio/904xBaseLogicx/..."
Is the presence of 904x logic expected in a 905x cRIO? Is there anything I can do to help prevent these errors in the future besides playing around with build settings and performing minor-tweaks to hope I can get the build to succeed? I am using < 50% of slices, so I can't imagine I'm asking too much of my FPGA here.
I checked the compatibility of your hardware and software and everything looks good there.
Are you seeing this error consistently with your code or only on some builds? Have you tried compiling a simpler code like a LabVIEW example to see if this error may be might be happening on other unrelated builds? Knowing all the different cases that we see this error can help us narrow down the root cause.
One good step here might be to Format Disk of the cRIO through NI MAX.
Hi TyVo, Thank you for your reply.
I am seeing the error only with some of my builds. Most of my builds (~70%) pass without issue, but occasionally one will fail. While this is not a show stopper, as I can usually get a successful build with minor tweaking and re-compiling, it is rather annoying.
If I had to guess, NI directly ported some of their code from the Kintex-7 based 904x series to the Artix-7 based 905x series. Some of that code only marginally passes on the slower Artix-7 fabric, and sometimes the Xilinx tools fail to meet the timing requirements when there are non-trivial amounts of user block-diagram logic to implement. Does this sound like a reasonable explanation to you?
How would formatting the disk of the cRIO affect whether or not I can successfully get my FPGA code to build?
I'm not personally familiar with the low level functionality of the compiler tools but it is Xilinx that makes the tools so I don't believe it would be an NI "porting" mistake.
NI does have some documentation to help programming for timing performance on FPGA: http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgaconcepts/optimizing_fpga_vis/
I hope that can provide some amount of help.