LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

FPGA sample clock match data

Solved!
Go to solution

Hi,

 

I have a question regarding FPGA sample clock. If the data that must be read match the sample clock rising edge, what would FPGA I/O node read? I attach an image for clarification.

 

Thanks,

Adriana.

"Overcome your challenges"

Adriana Oliva - DM Integrations
0 Kudos
Message 1 of 6
(391 Views)

Hi Adriana,

 


@Adriana-DMIntegrations wrote:

If the data that must be read match the sample clock rising edge, what would FPGA I/O node read?


That is rather undetermined.

Are you sure the internal FPGA clock and the external signal are the very same down to the picosecond/femtosecond range (in the time axis)?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO
0 Kudos
Message 2 of 6
(366 Views)

It's a theoretical question. If they would perfectly match, what would the FPGA I/O Node read. I guess that 1, if the clock triggers reading data on rising edge but I am not sure.

"Overcome your challenges"

Adriana Oliva - DM Integrations
0 Kudos
Message 3 of 6
(363 Views)
Solution
Accepted by topic author Adriana-DMIntegrations

Hi Adriana,

 


@Adriana-DMIntegrations wrote:

It's a theoretical question.


What's the practical use of this theoretical question?

 


@Adriana-DMIntegrations wrote:

If they would perfectly match, what would the FPGA I/O Node read. I guess that 1, if the clock triggers reading data on rising edge but I am not sure.


"Perfectly match" on the outside of your DAQ device or in the ADC internals? Current might flow fast, but is also limited to the speed of light: every millimeter counts!

(Theoretical answer: I guess you would read a 1 when the sampling starts with the trigger edge…)

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO
0 Kudos
Message 4 of 6
(360 Views)

In the ADC internals. But it's sufficient to know that it would be 1.

 

Thanks.

"Overcome your challenges"

Adriana Oliva - DM Integrations
0 Kudos
Message 5 of 6
(327 Views)

In theory it’s 1, in practice almost certainly 0. Every digital circuitry has something called minimum setup time. It’s the time that a signal needs to be present at the input before the active edge of the according clock/sample control that causes the input to be read.

That can sometimes be 0ns but it is usually a few ns or more. If that setup time is not observed the value that is read is very likely the previous value but the minimum setup time is a guaranteed value so the circuit may be faster (depending on power supply level, temperature and such).

 

Also note that the voltage level on which the clock switches does not necessarily have to be the same as the data input. Digital signals are in theory just 0 and 1, in reality (assuming TTL level for this exercise) 0 is a voltage between 0 and 0.8V and 1 is a voltage higher than 2.4V. That range between 0.8 and 2.4 is undetermined and one input may switch at 1.2 V while the other may switch at 2V

For 3.3V logic pretty much the same applies although depending if it is TTL compatible or not with slightly different ranges.

Rolf Kalbermatter
My Blog
0 Kudos
Message 6 of 6
(224 Views)