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Manzolli

Multi-core Compiling

Status: New

Even though ibberger touched the concept in the idea , I do think that most o people uses LabVIEW under Windows environment. Compiling a FPGA VI happens all in the PC under Windows. I noticed that during this process the compiler uses only one core. Since I'm using a machine with a 4 core processor, the CPU use rarely goes above 25%.

 

My idea is to update the compiler allowing it to be multicore. The user should have the option to limit the maximum number of cores available to the compiler. This is necessary because the user may want to continue working, while the compiling process is being done in background.

André Manzolli

Mechanical Engineer
Certified LabVIEW Developer - CLD
LabVIEW Champion
Curitiba - PR - Brazil
42 Comments
cbutcher
Trusted Enthusiast

Some brief comments for 2017 and 2018:

When compiling the same project (fairly simple) a few times, I got the following results:

 

Xeon E5-2680 (2.7GHz base, 3.5GHz max), 16GB RAM, Windows 10 64-bit Enterprise, Turbo Boost and Hyperthreading both enabled

 

LV2017, High priority and with a set Affinity (1 core) via the Details tab on the Task Manager: 10 minutes

LV2017, no affinity or priority changes: 8:49

LV2017 with the priority and affinity via Lorn's shortcut settings: 10:11 (6:25, 1:23, 1:21 Synth, Place, Route)

 

LV2018 (so 2017.2 Vivado) with default: 6:40 (4:06, 0:59, 0:45)

LV2018 with shortcut: 8:03 (4:12, 1:27, 1:17).

 

I didn't notice any particular change to the clock speed watching the task manager, in each case it sat somewhere between 3.1 and 3.2GHz.

 

These results seem to basically just confirm that Place and Route can be multithreaded in at least these versions of Vivado/LabVIEW FPGA, whilst the Synth time is both the longest and not particularly affected on my system by locking affinity.

 

I post them mainly because 2018 (2017.2) was significantly faster than 2017 (2015.4), so I might look at moving my project to 2018 and installing on the rest of the computers we use...


GCentral
Terry_ALE
Active Participant

Vivado has a setting for using multiple cores.  This is seen when running compiles are a Vivado Export.


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Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications