For Loop within Single Cyle Timed Loop

[Alex.T]

In current versions of LabVIEW FPGA, placing a For Loop inside an SCTL will result in code that cannot be compiled; this is because conventially For Loops work iteratively and therefore require multiple clock signals to drive each new iteration.

However, I think a logical implementation of a For Loop within an SCTL would be the generation of multiple parallelised instances of whatever code is inside the For Loop. This would greatly improve readability and flexibility by avoiding the user having to manually create multiple separate instances of the same critical code on the Block Diagram.

This would require the For Loop to execute a known maximum number of times.

[EricLM]

While for loops are now supported inside SCTLs, they lack some of the basic support for bit manipulation and unsupported elements do not result in a broken run arrow. Instead you don't find out until compile that they are not supported.