BRAM Primitives with different Read / Write data widths

[Intaris]

Xilinx supports BRAM primitives (FIFO and normal BRAM) with certain varying width read and write ports.  For some applications, the ability to write 2x 16 bit values to a FIFO in one loop and read 1x 16 bit value from the FIFO at double clock rate in another loop can be very useful.

As it stands, the IPCore for such BRAM primitives, although present in LabVIEW FPGA, cannot be used without a CLIP (essentially making this aspect of the IPCore useless).

It would be cool if LV would expose the ability to have differing read and write port widths for BRAM.