HW-timed vs SW-timed sequence

[AJ3D]

I ran both of the following examples:

NI-DCPower Hardware-Timed Voltage Sweep

NI-DCPower Software-Timed Voltage Sweep

on my PXIe-4141 SMU with the Source Delay set to 0.

I captured the voltage sweep on an a scope. I was surprised to find out that BOTH examples produced a staircase voltage ramp with the same delay between each step of about 17ms. I expected the HW-timed sequence to be much faster than the SW-timed sequence. (see attached screenshot)

How do you explain this observation?

Thanks

[ChrisR.]

Hi, AJ3D.  Here's another forum post that I think answers your question:

https://forums.ni.com/t5/PXI/Fastest-update-rate-for-source-operations-in-PXIe-4141/m-p/1923143/high...

And here's a list of attribute defaults for the PXIe-4140/41 http://zone.ni.com/reference/en-XX/help/370736U-01/nidcpowercref/supportedattributes4140_4141/ .  0.016...67 seconds shows up on a couple of different rows: aperture time and source delay.  You minimized only one of those.

Chris

[AJ3D]

Thanks Chris.

I learn something everyday.

However, I expected the SW-timed sequence to be slower than the HW-timed due to the overhead of CUP-to-SMU communication after each measurement step.

[kirsch]

> However, I expected the SW-timed sequence to be slower than the HW-timed due to the overhead of CUP-to-SMU communication after each measurement step.

It is slower (and also not deterministic), but not so much slower that it jumps out visually in a scope when each voltage is being held for ~17 ms. The time it takes the computer/driver to reconfigure the device is measured in microseconds.

[kirsch]

> However, I expected the SW-timed sequence to be slower than the HW-timed due to the overhead of CUP-to-SMU communication after each measurement step.