Digital I/O
NI 9201+ 9474 troubles
Hi,
The problem you're seeing is not from your FPGA acquisition, but in the way you retrieve those values on the RT VI.
In your FPGA VI, as you said, you removed the timing functions in the Analog acquisition loop, so your module is acquiring datas as fast as he can (wich should be around 300 kHz or more).
Then, those values are updated on the indicator, and the last value is erased each time a new value appears.
But, in your RT VI, you have a loop wich reads theses indicators with a Read/Write control node, and this is in a loop timed with a ms function. From what's I've seen on your screenshot, it was timed around 40ms, so you display a value every 40 ms in your graph, that's why your signal is not as good as you expect.
You should change your timing for faster loop rate in order to get better signals, but a risk is to consume CPU usage and get an instable VI. So you need to be carefull and to verify that the timing you choose is not too small for the loop.
Otherwise, you can set a timing in your FPGA VI, wich assure a constant sample rate, and use DMA FIFO for getting the values accurately on the RT target. You can have a look in the example finder for Hardware Input and Output>>CompactRIO>>FPGA Fundamentals>>DMA>>DMA Buffered Acquisition - cRIO.lvproj
Regards,
Hi Mario,
First, could you please give your complete project in a zip file instead of the different VIs. I could see some more details on target configuration and FIFO configuration.
Then, you have to verify several things doing this kind of tasks. First, your RT loop, as already said, can't run too fast because of CPU consumption, so you need to define a respectable loop rate. Then, you have to compare the RT Loop rate and your acquisition sample rate, in this way, you decide how much sample you need to read in your FIFO at a time. Then, you setup your FIFO size to be 2-3 times (at least) bigger than this number, and you should manage to acquire everything you need.
Regards,
Hi Mario,
I'm glad to hear that you are now able to measure a good signal.
About RT, you are actually using RT OS without knowing it:
In a Real-time project, you basically have three parts :
- The Host part, wich is your Windows computer, and is seen in the project as "My Computer". If you add a VI under My Computer, this one will execute on your Windows environment.
- Then, the RT part, is seen in your particular project as "CRIO - M", which is your cRIO controller. This one you installed LabVIEW RT on it, and is executing the LabVIEW RT OS (probably VxWorks in your case, but that doesn't matter). So there, your Host VI resides under this RT target, then, when you execute it, it's first downloaded on the RT cRIO controller, then executed directly on the RT OS, even if you can still see the front panel on your Windows computer.
- Finally, there is the FPGA part, "FPGA Target", where you create an FPGA VI, then compile it to create a bitfile wich will be downloaded on the FPGA component on the cRIO chassis.
I understand the confusion between RT and Host, because we are used to name the RT VI "host VI" because it actually hosts the communication with the FPGA.
I hope that's more clear now.
I advise you to have a look at the CompactRIO developer's guide, you could get really interesting informations for later developments.
Regards,
Hi Mario,
Sorry for the delay, I was on holiday.
I assume that you tried using a windows host VI.
You can effectivelly use a Windows VI for user interface, and off-line analysis, wich help releasing RT processor.
You have to think if your operations have to be deterministic or not.
Then, you can use network shared variable, or TCP/IP functions to transfer datas betweens the RT VI and the Windows VI.
Cheers,
