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NI 9201+ 9474 troubles

Hi,

i have an application that need's voltage measurements and a PWM input, i'm using a cRIO-9111 and the modules are the NI-9201 and the NI-9474 to do that.

I'm already capable of doing these to things but just one at each time, now i'm wondering to put them working together..i've already tried but it didn't work how i wish it did.

The acquisition was working to slow, it seems like i'm not having suficient points of my signal, to be honest i'd never understood the purpose of some waiting times inside of the wile loops and i decided to take them away and the response of the system becomes better but not enough.

If some one can help me understood the problem and how to regulate the acquisition to get a good signal view it would be great.

i'll attach the VI's i've used and a printscreen of what should be a 50Hz sine wave.

 

Thanks

M_Silva

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Message 1 of 11
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Hi,

 

The problem you're seeing is not from your FPGA acquisition, but in the way you retrieve those values on the RT VI.

In your FPGA VI, as you said, you removed the timing functions in the Analog acquisition loop, so your module is acquiring datas as fast as he can (wich should be around 300 kHz or more).

Then, those values are updated on the indicator, and the last value is erased each time a new value appears.

But, in your RT VI, you have a loop wich reads theses indicators with a Read/Write control node, and this is in a loop timed with a ms function. From what's I've seen on your screenshot, it was timed around 40ms, so you display a value every 40 ms in your graph, that's why your signal is not as good as you expect.

 

You should change your timing for faster loop rate in order to get better signals, but a risk is to consume CPU usage and get an instable VI. So you need to be carefull and to verify that the timing you choose is not too small for the loop.

 

Otherwise, you can set a timing in your FPGA VI, wich assure a constant sample rate, and use DMA FIFO for getting the values accurately on the RT target. You can have a look in the example finder for Hardware Input and Output>>CompactRIO>>FPGA Fundamentals>>DMA>>DMA Buffered Acquisition - cRIO.lvproj

 

Regards,

Olivier L. | Certified LabVIEW Developer


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Hi Olivier,

 

thanks a lot for replying my message, the problem are already half solved...but unfortunatley every time i reach a solution for a specific problem i found a ten more problems to solve, that's what keep this interesting but hard at the same time.

I'm now using DMA to transfer and read data buti still not have the speed i wish, to reach the goal i need to creat a 20kHz PWM signal (i already have it working) and i need to view the PWM signal and the output of the IGBT's wich i am not capable to do at this time =(

Now i can't view a rigth acquisition up to 5kHz, when i rise my signal frequency i also need to rise the frequency of the acquisition loop rate and that leads me all the time to an overflow..i've read some posts that said to rise the number of samples read too, and when i try to do that the flg of overflow is still getting on or my signal seems to be stoped because of the Time to Acquire Block that is obtained by (1000/acquisition loop rate)* nº of samples...and that's what i'm think that slow's my acquisition, am i right?

Let me know if you have some sugestion...(i'll attach the code i'm using now)

 

Thanks for help, have a nice day.

Mário Silva

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Message 3 of 11
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Hi Olivier,

 

thanks a lot for replying my message, the problem are already half solved...but unfortunatley every time i reach a solution for a specific problem i found a ten more problems to solve, that's what keep this interesting but hard at the same time.

I'm now using DMA to transfer and read data buti still not have the speed i wish, to reach the goal i need to creat a 20kHz PWM signal (i already have it working) and i need to view the PWM signal and the output of the IGBT's wich i am not capable to do at this time =(

Now i can't view a rigth acquisition up to 5kHz, when i rise my signal frequency i also need to rise the frequency of the acquisition loop rate and that leads me all the time to an overflow..i've read some posts that said to rise the number of samples read too, and when i try to do that the flg of overflow is still getting on or my signal seems to be stoped because of the Time to Acquire Block that is obtained by (1000/acquisition loop rate)* nº of samples...and that's what i'm think that slow's my acquisition, am i right?

Let me know if you have some sugestion...(i'll attach the code i'm using now)

 

Thanks for help, have a nice day.

Mário Silva

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Message 4 of 11
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Hi Mario,

 

First, could you please give your complete project in a zip file instead of the different VIs. I could see some more details on target configuration and FIFO configuration.

 

Then, you have to verify several things doing this kind of tasks. First, your RT loop, as already said, can't run too fast because of CPU consumption, so you need to define a respectable loop rate. Then, you have to compare the RT Loop rate and your acquisition sample rate, in this way, you decide how much sample you need to read in your FIFO at a time. Then, you setup your FIFO size to be 2-3 times (at least) bigger than this number, and you should manage to acquire everything you need.

 

Regards,

Olivier L. | Certified LabVIEW Developer


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Message 5 of 11
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Hi Olivier,

thanks again for answering..i already this mornig start a new project, like the one that i've done yesterday, i am now capable of acquiring 10kHz PWM signal with a nice quality..

When you say "your RT loop" you mean my Host loop?? I thought i'm not using the Real Time yet, i always start a FPGA project..i'm i wrong?? How can i control my Host loop?? sorry if i'm asking you some stupid question but this kind of connection between FPGA, Host and RT mess me a bit..

I'll attach the project for you to see.

 

Thanks a lot

Mário Silva

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Hi Mario,

 

I'm glad to hear that you are now able to measure a good signal.

About RT, you are actually using RT OS without knowing it:

In a Real-time project, you basically have three parts :

- The Host part, wich is your Windows computer, and is seen in the project as "My Computer". If you add a VI under My Computer, this one will execute on your Windows environment.

- Then, the RT part, is seen in your particular project as "CRIO - M", which is your cRIO controller. This one you installed LabVIEW RT on it, and is executing the LabVIEW RT OS (probably VxWorks in your case, but that doesn't matter). So there, your Host VI resides under this RT target, then, when you execute it, it's first downloaded on the RT cRIO controller, then executed directly on the RT OS, even if you can still see the front panel on your Windows computer.

- Finally, there is the FPGA part, "FPGA Target", where you create an FPGA VI, then compile it to create a bitfile wich will be downloaded on the FPGA component on the cRIO chassis.

 

I understand the confusion between RT and Host, because we are used to name the RT VI "host VI" because it actually hosts the communication with the FPGA.

 

I hope that's more clear now.

I advise you to have a look at the CompactRIO developer's guide, you could get really interesting informations for later developments.

 

Regards,

Olivier L. | Certified LabVIEW Developer


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Hi Olivier,

 

thanks for help me to clean a bit these messy  ideas that i got about this stuff...i haven't tried anything yet since my last post a few hours ago, i just arrive from lunch to another LabVIEW's afternoon, but with all you said i just got an idea....

can i put the numeric indicators and controls as like as graphics and some math operations to run in a VI over my computer in order to  release the RT processor ?? do i gain with this?

 

Thanks

Have a nice day.

Mário Silva

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Message 8 of 11
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Hi Mario,

 

Sorry for the delay, I was on holiday.

I assume that you tried using a windows host VI.

You can effectivelly use a Windows VI for user interface, and off-line analysis, wich help releasing RT processor.

You have to think if your operations have to be deterministic or not.

 

Then, you can use network shared variable, or TCP/IP functions to transfer datas betweens the RT VI and the Windows VI.

 

Cheers,

Olivier L. | Certified LabVIEW Developer


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Hi Olivier,

 

thanks for answering, don't worry about these kind of delays...we all deserve it..=)

i took a look at the CompactRIO Developers Guide, as you told me to, and i found it interesting.

Unfortunatly i'm running out of time cause i have my first presentation at middle of the next month and i feel more confident with the kind of block that i'm using now, i hope to optimise the code at the second part of my work. I was reading about pipelining and i already put it to work, i also was reading about scaling my channels but i can only run my first channel, don't know what's wrong with the others. Another problem is that i still get a signal that is not the one that i get in my scope, i'm running a 10kHz PWM with my NI-9474 and i see it well at scope but when i acquire it it doesn't seems so good, i'll attach a picture for you to see.

 

Thanks Olivier

Regards

Mário Silva

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