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NI-5421 PFI Capabilities for Valid Signal Sync

Hi All. I was wondering if anyone could help me answer a few questions I had with the NI-5421 PXI card. Briefly, my application uses all 16 bits of data to generate an arbitrary waveform from a saved image file. I am using the DDC connector, and am bringing in a 28MHz reference clock on the CLK_IN pins. First Question:

 

How easily can this clock be divided down by 4 to 7MHz, to drive the AWG Image? Right now I needed to do a workaround and take that image file and multiple each line of data by 4, essentially making it 4 times as long in order to simulate the 7MHz data rate. I have seen the 'Sample Clocking' and 'Reference Clocking' terms thrown around in the documentation, however I know that I am not implementing this correctly. 

 

Second Question, is the headache of understanding what I can do with the PFI 4&5 pins. Essentially, I need a "Data Valid" or a Sync Signal that stays high for ~11 milliseconds while the image data is flowed out of bits 0-15, then goes low for ~3.3 milliseconds. Overall it is that periodic signal that is repeated at 70Hz (~14.3 milliseconds), however I am having trouble understanding if a marker event can remain high for that length of time. Just to note, the "Sync" part of the signal is actually when it is driven LOW, however the image should be generated with a negligible delay on the rising edge of the sync signal. Therefore I was wondering if a marker event at offset 0 ( by adjusting the marker event pulse width) could in fact be held high and operated in this fashion over 70Hz. Otherwise, I will have to use an external FPGA to work this sync signal and then provide a start pulse over the PFI 2&3 channels to step through image data. 

 

I decided to not attach any code right now because I am first just trying to understand this card's capabilities. Please let me know if there is more clarification on any topics needed, but the main questions I need answered are 1. Can a 28MHz clock being brought in on the DDC CLK_IN pins be divided down to 7MHz and THEN drive the output of the AWG Image file? 2. Can the PFI 4&5 output pins be held HIGH for long periods of time, or at least for 11ms? 

 

Thank you so much for any help you may be able to provide. -Ed 

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How easily can this clock be divided down by 4 to 7MHz, to drive the AWG Image? Right now I needed to do a workaround and take that image file and multiple each line of data by 4, essentially making it 4 times as long in order to simulate the 7MHz data rate. I have seen the 'Sample Clocking' and 'Reference Clocking' terms thrown around in the documentation, however I know that I am not implementing this correctly. 

 

I could be wrong about this (it's been a while) but I don't think you can divide an external Sample Clock. You might be able to use it as a Reference Clock, and then use the internal DDS to configure the device's Sample Clock to your desired values. Read back Sample Clock after all the configuration is complete to get its "coerced value". This is important because if the device uses its high resolution clock, it may not be able to exactly hit the frequencies you want, but it will be very close - which means you'd see some drift.

 

Second Question, is the headache of understanding what I can do with the PFI 4&5 pins. Essentially, I need a "Data Valid" or a Sync Signal that stays high for ~11 milliseconds while the image data is flowed out of bits 0-15, then goes low for ~3.3 milliseconds. Overall it is that periodic signal that is repeated at 70Hz (~14.3 milliseconds), however I am having trouble understanding if a marker event can remain high for that length of time. Just to note, the "Sync" part of the signal is actually when it is driven LOW, however the image should be generated with a negligible delay on the rising edge of the sync signal. Therefore I was wondering if a marker event at offset 0 ( by adjusting the marker event pulse width) could in fact be held high and operated in this fashion over 70Hz. Otherwise, I will have to use an external FPGA to work this sync signal and then provide a start pulse over the PFI 2&3 channels to step through image data. 

 

Like you said, you can use one of the four available Marker Event routed to PFI 4 or 5 for this. In order to hold the Marker Event high configure it to "Toggle" and in your script assert it once to go high and once again to go low.

 

Good luck, I'll be curious to hear if you were successful with this.

 

 

Marcos Kirsch
Chief Software Engineer
NI Driver Software
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