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park and inversepark transform take all the resoureces


I'm new to Labview FPGA, and I'm using sbRIO9606 to do some experiments. I have a problem with the high throughput sin-cos function. When I use this to do a park and inverse park transformation.  It takes all the LUTS resources in FPGA as in the FPGA vi: PWM test.vi

So I tried to put the park and inverse park transformation in the RT and transfer the data back to FPGA. At first I use the direct FPGA read/write function in the RT however, it gives me some results but not right.

Then I try to use FIFO to pass values between RT and FPGA, but I cant configure them the right way.

In the project the PWM test.vi is the one I put everything in FPGA

im_communitert.vi is the vi I tried to pass the angle generated in FPGA to RT and  the rt_IMcontrol.vi is the RT host vi

Can somebody please help me out?


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Message 1 of 14


in abctoqd.vi you did not use high throug. function. sin and cos are implemented in double, which must be strongly avoided in FPGA. Even if the result is converted in FXP, evaluation is performed in double.

I closed a field oriented control loop on NI myRIO. Programming should be efficient, in the FPGA resources are very limited.

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Message 2 of 14

thank you for the reply, is that ok that you send me the park and inverse park vi you use ?


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Message 3 of 14

You can download resource efficient IP Builder versions of all of the most common transforms for power electronics here. Big thanks to NI systems engineer, Brian_K, for these!

This free, open source library includes efficient floating point (and fixed point versions) of the following transforms:

  • ABC to DQ
  • DQ to ABC
  • ABC to alpha, beta (Clarke Transform)
  • alpha, beta to ABC (Inverse Clarke Transform)
  • alpha, beta to DQ (Park Transform)
  • DQ to alpha, beta (Inverse Park Transform)
  • sine and cosine


  • In all of the functions, the units for theta are pi*radians rather than radians. In other words, set theta = 1 to represent an angle of 180 degrees or pi radians. Set theta = -0.5 to represent an angle of -90 degrees or pi/2 radians.
  • The compiled IP cores suitable for embedding in your LabVIEW FPGA control applications are located in LabVIEW Project under the FPGA Target>IP Builder Generated VIs folder. See the IP core subVIs highlighted in blue in the first screenshot below. Drag these into your control application to use them.
  • To use the generated IP cores for the sbRIO-9607, you do not need to have the Xilinx Compilation Tools installed. However, to regenerate the IP (i.e. to apply different constraints), you need to have the Xilinx Compilation Tools installed and be running Windows 7 (ISE for sbRIO-9606, Vivado for sbRIO-9607). The Windows 7 requirement is a Xilinx toolchain limitation- sorry.
  • The cores are set up in the project for the sbRIO-9607 (Zynq-7020). They can be converted to sbRIO-9606 (Spartan-6 LX45). After moving them, you'll need to regenerate the IP.
  • A nice feature of IP Builder is that you can estimate the resource usage without compiling.

To learn how to use IP Builder to create highly resource optimized IP cores for LabVIEW FPGA, see this whitepaper. Please reply to this thread with any questions.

Here are screenshots:

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10-26-2015 3-12-29 PM.jpg

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10-26-2015 3-13-29 PM.jpg

10-26-2015 3-14-06 PM.jpg

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Message 4 of 14


attached the tranformations I used with myRIO.

Avoid single or double arithmetic, I used FXP to save FPGA space. If you correctly size the FXP, rounding effects are negligible.


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Message 5 of 14

Thank you for sharing these VI, one question is Im currently using 9606 in labview 2014. could you please give some details about how i can use this VI in labview 2014

Another question is I’m using the math script node on RT to do some matrix manipulation. I wonder is there a way that we can somehow generate a FPGA executable VI from the math script node ?



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Message 6 of 14

thank you

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Message 7 of 14


looks like you do your contorl on the RT level, which i have lots of problmes to do it.

In my control i have everything done in fpga level.

Initially, i want to only use the ADC and DIO on FPGA and get all the control done on RT level, however i have some many problem with the data transfer between RT and FPGA.

I still get it done on FPGA level(as the code attached https://drive.google.com/file/d/0B5gS1H0brOGgQW0wVFVTZ24wY0U/view?usp=sharing) However, if you can show me how you get the data transfer between RT and FPGA it will be great

Thank you



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Message 8 of 14

No, no,

high speed loops are closed on the FPGA, mainly in FXP: dq-axis current controllers for instance.

Data transfer between RT and FPGA is not so fast to allow you to close high bandwidth controllers on the RT target.

With respect to the FPGA model, this is one of the powerfull characteristics of LabVIEW: the source code is highly "uncorrelated" to the hardware where it will be executed. You mainly need to setup output pins...

"I wonder is there a way that we can somehow generate a FPGA executable VI from the math script node ?"

I really do not know, neverneeded this specific feature. You can do in the RT target: there are some specific blocks.

The VI I uploaded are designed to be used in the FPGA, put them in your FPGA VI: see help for more info.



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Message 9 of 14

thank you

now my main problem is i want to do a matrix inverse on FPGA level, i wonder if you know how to do that

thank you

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Message 10 of 14