PXI unstable outputs

[CSU_Chris]

I have a PXI system with a PXIe-1088 chassis and a PXIe-8822 controller. The system modules include a PXIe-4303 analog input card and a PXIe-7846R FPGA. 

The system is being used to control a motor test stand. The PXIe-8822 is sampling a lot of analog instruments via the PXIe-4303 and running an open-loop volts per hertz control algorithm for the motors. The analog sampling and motor controls are running in separate, independent timed loops. The sinusoidal duty cycles calculated on the PXIe-8822 controller are sent to the PXIe-7846R FPGA which does a standard sine-triangle PWM to control the timing of the IGBT gate signals in the motor drive. 

I have noticed that when I push the analog sample rate higher (up to the 50 kS/s limit of the card) the motors start to run rough. The motor torques and speeds start to jump around and an oscilloscope shows that the motor currents become distorted and are no longer sinusoidal. The only way this could happen is if the duty cycle for the switches deviates from the nominal sine wave.

I would expect the PXIe-7846R to be pretty robust, given it is an FPGA. My suspicion is that there is an internal data bus limit within the PXIe-1088 chassis that when I increase the analog sample rate it causes a latency in the duty cycles reaching the FPGA. However, none of the timed loops indicate that they are ending late and the CPU loading is staying in the 20-40% range for all four cores.

I am including my real-time and FPGA codes, although this is rather large code with a lot going on so it may not be helpful to someone not familiar with our test system. I'm also including some oscilloscope plots showing good and distorted current waveforms.

[ZYOng]

Next time please attach the entire project including .lvproj file. It saves our time to create a new project to add your VIs.

Since you suspect that it might be a bus bandwidth issue, try inserting your modules in slots 4,6 or 8 only. Those slots have access to the full x4 bandwidth, whereas the remaining slots share a single x4 lane through a PCIe switch.

[CSU_Chris]

Thank you for your very helpful reply. I was unaware that certain slots had the x4 bus for those slots so that is good to know. Upon further investigation is appears the issue may be related to timing jitter on the PXIe-8822 controller. The loop that is computing duty cycles is supposed to be running at 167 us but the actual loop cycle time varies quite a bit. Any ideas on where timing jitter might be coming from when running timed loops on a PXI?

[CSU_Chris]

Following up with more info. Attached are plots showing the control loop execution time with different analog sample rates. The loop is supposed to execute every 167 microseconds (us). When I have a 100 us sample period (10 kS/s/ch) the jitter is present but not too bad. When I decrease the analog sample period to 20 us (50 kS/s/ch) I regularly see loop cycle times exceeding 600 us and some exceeding 700 us.

The AI sample loop and the motor control loop are in separate timed loops on separate cores with no dependencies between them.

I checked the CPU/memory usage while running using the distributed system manager and all four cores are < 50% load and memory usage is < 1 GB.

Any ideas why increasing the analog sample rate would cause the control loop to run so much slower? Is there some other shared resource that's getting overtaxed that I'm not seeing?