NI VeriStand FPGA-Based I/O Interface Tools Discussion

[StephenB]

Nevermind, the latest version 1.2 was posted with this fix for all versions as well as 2012 support

[IsGa]

Hi StephenB,

Sorry for the late reply.

I don't get the error when I open an FPGA project. I also get the error then I discover by IP adress the board in the NIVS project.

But don't worry, I solved my problem by starting from NIVS project already done, with all the VI from the VS Tools, Engine Simulation, ... that I need.It works fine 🙂

I have also a question about DMA FIFOs, just to be sure. The number of DMA FIFOs is usually limited to 3, isn't it ? As the I/O tools are using 2 DMA FIFOs, there is just one more available ?

In the LV project, it looks like there is no limitation about the number of DMA_FIFOs. What happends then ? A compilation Error ?

I am already using 2 DMA FIFOs for the VS I/O Tools and one other for the VS Engine Simulation Custon Device.

I would like to add a cRIO CAN module to the sbRIO (9642), I do not know exactly how it works with LV FPGA, VS and X-NET, but I am already worried about DMA FIFOs...

Regards,

Isabelle

[StephenB]

Hi Isabelle,

Most FPGA devices only support 3 DMA FIFOs. You can define as many as you want in the project, but cannot use more than 3 in your code (including the one used "in the background" by XNET modules). You will get a compile error.

Yes, the template uses two DMA FIFOs and XNET uses 1. So there are no DMA FIFOs remaining. However, the engine simulation custom device and automotive engine simulation library was updated about a year ago to no longer need a DMA FIFO. Make sure you're using the latest verison.

[StephenB]

Also, the XNET CAN modules are not supported on sbRIO. You will need a different controller. Check ni.com for a list of supported controllers for XNET C series modules.    

[IsGa]

Hi Stephen,

Thanks for your answer ! I have got a NI 9852 CAN module (no XNET),

I experience a bug using the I/O Tools, and I would like to have more informations about it.

Here is my configuration :

Hardware : sbRIO 9642

Software : Labview 2011 SP1 (RT, FPGA), NI VS 2011 SP1

On my FPGA VI, I have the NI VeriStand FPGA-Based I/O Interface Tools and also the Engine Simulation Custom Device. In order to minimize the size of my FPGA VI (FPGA was going to be full) I changed the "PWM In Timeout" controls into constants (the PWM In loop is provided by the I/O inferface tools).

Here is the modified loop :

The FPGA VI compiles. But in NIVS, when I add the FPGA ( *.fpgaconfig), I have this error :

It looks like NIVS is searching for the PWM timeout controls and can't find it (of course I turned it to constants ^^). Why does this control has to be identified by VS ? In order to minimize the size of the code, I also chaged the PWM Out Control into a global variable, it works fine with NIVS :

So I don't really get why I have this error for the PWM timeout controls...Which généric elements can from the I/O Tools can be modified whitout creating any troubles in NIVS ?

Do you know this problem ? Can you tell me more about how NIVS communicates/recognizes an FPGA VI ? I was convinced that it was thanks to DMA FIFOs and how packets are defined in the *.fpgaconfug file, but ...

Best regards,

Isabelle

[StephenB]

It is looking for the control named _PWM In 0 timeout because that is defined in your XML:

                <Parameters>
                    <U32>
                        <Name>Time Out [ms]</Name>
                        <ControlName>_PWM In 0 timeout</ControlName>
                        <InitialValue>10</InitialValue>
                        <Scale>107374.182375</Scale>
                    </U32>
                </Parameters>

You can delete this from your fpgaconfig file

[IsGa]

Dear Stephen,

Thanks a lot, I completely skiped that part ok the .fpgaconfig file....

I am currently upgrading to NIVS2012. I have the following issue during the deployment onlu when there is an *.fpgaconfig in my SDF :

....

• Starting deployment group 1...
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:
Error -61201 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

This error code is undefined. Undefined errors might occur for a number of reasons. For example, no one has provided a description for the code, or you might have wired a number that is not an error code to the error code input.

Additionally, undefined error codes might occur because the error relates to a third-party object, such as the operating system or ActiveX. For these third-party errors, you might be able to obtain a description of the error by searching the Web for the error code (-61201) or for its hexadecimal representation (0xFFFF10EF).

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
• Sending reset command to all targets...
• Unloading System Definition file...
• Connection with target Controller has been lost.

I don't really find anything searching for the error code.... Do you have any idea about this issue ?

Best,

Isabelle

[StephenB]

Hey IsGa,

I get this description for that error:

Error -61201 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

LabVIEW FPGA:  The chassis is in Scan Interface programming mode. In order to run FPGA VIs, you must go to the chassis properties page, select FPGA programming mode, and deploy the settings.

Go to the controller and change the scan mode setting to FPGA. Should fix it!

[Jiri_K]

Isabelle,

I have already answer the question by email. I didn't know about the forum.

Could you please use only one of the resources, so we don't duplicate the effort with my colleagues.

Regards,

Jiri

[IsGa]

I am so sorry, I didn't realized you were both working on this thread...

Best,

Isabelle