PCI-6115 external Sample Clock

[MumenRiderT]

I'm using a waveform generator outputting square wave to provide PCI-6115 an external clock on pin PFI 7.

This clock is used in a Voltage Input vi .

Now that I can get a 1M sample rate from a 1MHz square wave, I still wonder when do I get a sample in a clock period, rising edge or falling edge or other ?

In reference to PCI-6115 pinout, high/low change of the external signal represents a sample, but in a square wave period there're 2 changes, that's what confused me

[Kevin_Price]

That's configurable (in LabVIEW anyway) with a DAQmx Timing property node.  Look for "Sample Clock-->Active Edge".  I think a lot of devices default to rising edge when not explicitly specified.  But if it matters to your app, you can set it programmatically before starting the task.

-Kevin P

[MumenRiderT]

With your help I've confirmed what edge I used.Thank you.

And can I ask another question that how to output my colck signal. Infered from pinout , PFI 7 can do. But I don't know whether I need to do extra work in the program. Because I have detected signal from PFI 7, and it has similar frequency feature with the colck signal, but with huge noise. I'm not sure about whether it is the right one.

Again, thank you.

[Kevin_Price]

If a TTL (0-5V) clock-like signal at your chosen sample rate can be seen on PFI 7, you're program's already doing what it needs to do.  Are you getting a TTL-like output amplitude (in the ~3-5 volt range) for the clock?

Try disconnecting all external connections from PFI 7 -- does the clock signal coming out to PFI 7 from the DAQ device look a lot cleaner (less noisy) now?

-Kevin P