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Combining Multiple Analog Inputs to form an Analog Output

I need to combine two analog input measurements to form a single analog output measurement. What is the best way to do this?


One signal is a 46 kHz square wave. The other signal is a 100 Hz square wave. I want to send an output only when both signals are high.


I have used daq-mx to measure analog input signals and to generate user defined analog outputs, but I cannot figure out how to combine analog inputs. I've currently using an NI-USB-6363 device. Speed is important for this task. Can I do this with daq-mx or is it better to use an NI FPGA device? 

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Message 1 of 7

Considering the 46kHz, that is a too fast to reliably do in Windows.  Even RT might struggle.  So I would go with the FPGA route.  And since you are dealing with square waves, you might want to consider Digital IO instead of Analog IO (makes the processing easier, especially in FPGA).

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Message 2 of 7

Condition them to logic levels and use and AND logic gate is what I would do. No DAQ card required.



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Message 3 of 7

Thank you for the replies.

I agree it makes more sense to use Digital IO than Analog IO.

The output signal is more complicated than I initial indicated. I figured if I could understand how to combine 2 signals, I would be able to scale it up to multiple signals. I made a diagram showing the full scope of the problem I'm working on. There are 5 input signals. The output signal is a combination of the 5 signals. The application is the triggering of an intensified camera. I need to trigger the intensifier at a different frequency during each 10 ms period. During the first 10 ms period I trigger the camera at 46 kHz. During the second 10 ms period I trigger the camera at 40 kHz, etc., as shown in the figure.

I'm not sure if this complexity precludes the use of logic levels and an AND gate. My apologies, I'm not an expert in this area.

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Message 4 of 7

I recommend external logic, i.e. TTL (cheap)  74LS253 4-line to 1 line selector. Drive this from a 2-bit counter clocked by the rising edge of your 100 Hz input. Finally AND with your 100 Hz input to get output only when your 100Hz signal is high.


Are all 5 signals derived from a master clock? What EXACTLY do you want to happen when a rising or falling edge of one of your 20-46kHz clock signals occurs within 1nS of a rising or falling edge of your 100Hz multiplexer signal? Short runt-pulses of this sort can cause chaos as they may not create consistent behavior in the downstream circuits, as they will vary in amplitude and duration.



Message 5 of 7

That is a good idea, but I'm not sure if it gives me a flexibility that I need to switch between the different waveforms.


The signals do not share the same master clock. The timing of the 100 Hz signal is synced with my experiment. The other signals are output from the controllers of our photo-elastic modulators (PEMs). There are 2 PEMs, each with its own controller. Each controller outputs its driving frequency and the 2nd harmonic of its driving frequency. So one controller outputs 20 and 40 kHz. The other controller outputs 23 and 46 kHz. These signals are free running and not synced to anything outside of a given controller. These four output signals (20, 23, 40, and 46 kHz) are TTL signals.

During the first 10 ms when the 100 Hz signal is high: I want an AND gate between the 100 Hz signal and the 20 kHz signal.

During the second 10 ms when the 100 Hz signal is high: I want an AND gate between the 100 Hz signal and the 23 kHz signal.


The output of the combined signals will be used to trigger the intensifier of my camera. I am planning to trigger on the rising edge, but I can just as easily trigger on the falling edge.

Anything less than 100 ns of jitter is sufficient for my application.


Thank you for your interest.

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Message 6 of 7

So I'm the third one that would use TTL ICs

a 4 to 1 MUX , a divider (or two FF) for channel select , controled by the 100Hz and finally the AND gate.


Or use a myRIO(?) FPGA to do all that logic  or a 40MHz 32bit 20$ ARM board or your flawor and do some interrupt programming .... but migth end with unwanted delays but 100ns is no problem.


or, for of the 5ms pulsetrain (10ms periode , but half of it is 1!) you can use 5 AND gates (or the 4 to 1 ... ) and do the select with the DO of a DAQ (stream , triggered by the 100Hz falling) and gain software control (by the byte stream of the DO) of the channels.

but you will never know the duration of the fist and last pulse in one pulsetrain... (unless you use an FPGA, estinate the kHz frequency  and use the slopes instead of level .. and cut the first and last) 


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Message 7 of 7