06-18-2018 09:05 AM
I work with Labview FPGA
I send a sinussoidal signal on the AI0 module, on the oscilo I see the complete and perfect signal, but on the graph of labview I do not visualize my signal!
06-18-2018 09:17 AM
which kind of FPGA do you use? I don't know any supporting an (interactive) user interface with charts/graphs…
Did you examine the example projects provided by LabVIEW? Those examples explain how to transfer data from FPGA to RT host to PC host!
06-18-2018 09:20 AM
i 'am using labview fpga 2017 , NI PXIe_1082 and NI 7583 Adapter Module
I dont want to transfer data to the Host , i want to see them on the vi target !
Is that Possible ?
06-18-2018 09:27 AM - edited 06-18-2018 09:27 AM
06-19-2018 02:45 AM
Ok , Thank you !
06-19-2018 05:17 AM - edited 06-19-2018 05:18 AM
Probably a completely unneccessary interjection but....
The following post assumes you are trying to run your VI in interactive mode. If this is incorrect, discard the entirety of all that follows (well, my post at least).
It IS possible to use graphs on an FPGA FP like you want. Charts don't work, and I'll try to elaborate why.
When you place a control on the FP of an FPGA VI, it will update much slower than the FPGA can update, this should be obvious. If I have an I32 on the FP of my FPGA VI, I might see "fast" updates of 60Hz (all my monitor can handle) but it may also be significantly lower depending ont he overall complexity of the UI ont he FP of my VI. The reason for this is that there is an inherent polling of the control on the FP (similar to accessing controls via FPGA reference) and this is non-deterministic and relatively slow compared to what the FPGA is actually doing. So, if you have a graph, a graph is actually a single value, say I32. The time delay between updating each individual element will be varied and will be relatively slow. Think of an irregular sampling of your waveform and displaying this on a uniform X-axis on your UI. This won't be pretty.
So why do Graphs work? A graph is an array. By handling the array on your FPGA (either using it as a ring buffer or triggering updating the data within), you generate an array data type with deterministic, FPGA-based timings. When your code polls the FP control, it polls the array which maintains the timing between the individual points. LV FPGA guarantees that clusters and arrays are transferred atomically. You won't see many points (Arrays are really expensive on FPGA) but it CAN prove useful for debugging. It's also quite a bit of work to get the array handling implemented efficiently so that just adding a 64-element array on your FP doesn't consume silly amounts of your FPGA fabric.