I would like to launch FPGA compilationS during the night. I tought about building a tool based on Project API which would launch the compile process (as the right-clic -> compile does). With this API I can find the VI but I haven't any method allowing to launch the compilation. One solution would be to execute the VI to launch the compilation process and then abort exec when the VI is running (it means that the compilation is succesful) (??) but it requires that the target is connected to the computer in order to deploy the bitfile.
Is there a to programmatically launch the compilation in the same way as the right-clic -> Compile does ?
Solved! Go to Solution.
Following this post, we used the same niFPGACompileVi.vi for our overnight compiles under 2009. After the recent upgrade to 2010, now the vi is missing. Do you know where it went and how we can get the overnight compiles working again?
As Donovan explained in his post "the Compile subVI is not on the LabVIEW palette and may not work in previous or future versions of LabVIEW FPGA". Moreover, the compiler interface has changed between LabVIEW 2009 and LabVIEW 2010. From now you need to create Build Specification to be able to compile you FPGA VI.
I do'nt know if Donovan can help you to implement a VI to compile FPGA VI as it was done in LabVIEW 2009 with my VI.
Senior LabVIEW Developer @Neosoft
Yes, I realized this from actual experience 🙂
So is there a way to trigger Build Specs to build through VIs? This would work for us too. Thanks.
I tried doing this with the LabVIEW 2010\vi.lib\AppBuilder\BuildTargetBuildSpecification.vi, but it doesn't seem to work for FPGA build specs. It returns no error, but it also does nothing. It does spend a second or two deciding to do nothing, though.
Any other ideas how to accomplish this?
I've thrown together something that works for me to build multiple FPGAs in multiple projects with multiple build specs for a single VI. In my case, I build the same VI for several targets and with different Conditional Disable Symbols, so I have to resave the top-level VI in the context of the target I'm about to build. It could be improved to find all the dependencies and save them, in case there were Conditional Disable Structures in subVIs as well as the top-level VI.
It's not pretty and it may get at references less directly than possible. Any clean-up suggestions on the VI Server code is welcome.
Hope this helps,
It's been quite some time now... does LabVIEW 2018 or newer have an fully supported method for programmatically compiling VIs with LabVIEW FPGA?