When you simply close a loop in your diagram your wire becomes member of a cycle. The LabVIEW error you get if you try to run the VI says:
"These wires form a cycle, making two parts of the diagram interdependent, so each must wait for an input from the other and neither can execute."
You are dealing with a sample system and not (like an analog system) with a continuous system. So an output value fed back to the input can only be used in the following iteration.
The solution: Your system need to be included in either a While or a For loop (if it is not already the case) and then you need to create a shift register SR (right click on the edge of your structure and add shift register). Connect the output of your system to the right terminal of the SR and the f
eedback input to the left terminal of the SR.
Note again that you are then dealing with a sampled system (more like a z-domain model) so if you are trying to simulate an analog loop (s-domain) you'll see some variations from what you may expect the higher the system bandwidth is. Make sure to sample with s sufficient "time" resolution.