how to use the discrete unit delay block with the waveform as the input data type?

[nozombie]

Hi,

I'm using LabView 2011 to implement a design system. I want to first downsample the input signal and then go through the discrete unit delay function. However, after the unit delay function, i don't get the right output, is there a way to fix that?

The input is fixed to be the simulate signal since i'm using it for other implementation as well and i don;t want to change it.

plz see the attachment , thx!

[Norbert_B]

I am not sure if this could be a reason but it is possible that your delay does not match the "sample period" as a multiple.

Looking into the provided example SimEx discrete unit delay.vi, installed with the Control Design & Simulation module, does it work on your machine?

Why did you choose not to elaborate this example to your needs?

Norbert

PS: Your subVI SI Down Sampling.vi is missing

[timtamslam]

Hey nozombie,

Like norbert mentioned before, using the examples is a good start. Also, could you possibly elaborate a bit more on "I don't get the right output"? What output are you seeing and what are you expecting to see?

Hope to hear from you soon!

[nozombie]

Hi there,

I use the example and it works. However, i don't want to use the input type in the example. Instead I want to use the simulate signal sinewave as the input. When I can the input, I can't get the correct delay dispalyed on the graph.

Ivy

[nozombie]

Hi Tim,

As I said before, I don't want to use the input in the examples. So basiclly what I want to do is change the input I want and go through the same process. Finally what I want to see is the original downsampled signal and the delayed downsample signal displayed on the same graph =).

Ivy

[timtamslam]

Howdy Ivy,

it seems like, based on your first set of code, that you're interested in using the Simulate Signal Express VI instead of the signal generator in the Control Design palette. Here's an image of how I would configure it to get the Express VI working correctly. All that you should need to add is "Convert from Dynamic Data" and set the resulting type to Single scalar.

Using this method I am able to show the delay correctly.

Is there a particular reason why you want to use the Express VI over the standard Signal Generator VI or the Sine Waveform.vi?

[nozombie]

Hi Tim,

Thanks for replying!

What u did is exactly what I want except that I want to downsample the simulate signal first before I put it into a delay block.

I tried what u said, however, it only works for very small frequency such as 0.01 Hz. When I set the input to 10 Hz, the delay block doesn't work at all. For the diagram u have, what is the input frequency u set to the simulate signal?

The reason I'm use the Express VI is because I use it as the input of the frequency estimation block. So basicly what I'm doing is :

sine wave ->downsample it->delay the downsampled signal and do some numerical calculation(adding,multipling) ->estimate the frequency of the output signal -> this frequency is used to determin the sample factor in the downsampling process.

I attached the VI with the downsamped involved

I can't copy the downsample.vi because I use the evaluation version 30 days for that toolkit .

I attached the VI for frequency  estimation as well.

Thanks so much!

Ivy

[timtamslam]

Hey Ivy,

I think what's causing the biggest problem in this circumstance is the use of the Simulate Signal express VI. The express VI is designed to build an entire signal within one iteration. Currently the way the Simulate Signal Express VI is configured in the Testing.vi is that its building .01Hz signal which consists of 10000 points.

You can prove this by using the Convert from Dynamic Data function configured as "1D array of scalars - single channel" to convert the output of the Simulate Signal VI to an array of doubles. We can then check the size using the Array size function. You can also explore the basic functionality of the Simulate Signal VI within the Detailed Help. I also recommend the "Express Filter VI" example VI.

This overall setup is causing a problem for us within the Simulation Loop because the each simulation function (Discrete Unit Delay) in the Simulation Loop is only expecting one value at a time. Within the simulation environment we are creating a disconnect between the discrete time step between each loop iteration and the output of the Simulate Signal.

I highly recommend building off of an example which implements the  Signal Generator VI or the Sine Signal (Control Design & Simulation > Simulation > Signal Generation) native to the Control Design & Simulation setup in order to avoid these complications. I don't really see a necessary reason to use the Simulate Signal Express VI in this case as it overcomplicates the simulation process.

If you build off of the Examples I think it will help you save the most time and get to a resolution faster!

Have a great day!