difference between usage of block memory type FIFO and Flip-flop type FIFO

[anurocks]

Hi all

What is the difference between  application of block memory type FIFO and Flip-Flop type FIFO when using in FPGA vi?

Please help me to clear above doubt.

Thanks

Anurag 

[AdnanZ]

Click on the Help in the same page. If you have any specific questions, please let me know. Here is the link:

General Page (FIFO Properties Dialog Box)

Here is the explanation:

Flip-Flops—Stores the data in flip-flops available on the FPGA and provides the fastest performance. National Instruments recommends using this option for small FIFOs, up to 100 bytes. You cannot use FIFOs with an Implementation of Flip-Flops or Look-Up Table across multiple clock domains.

Block Memory—Stores the data using embedded blocks of memory. Xilinx literature describes this implementation as block RAM or BRAM. National Instruments recommends using this option for FIFOs larger than 300 bytes. If you select the Block Memory option, you might not be able to read data in a target-scoped FIFO or VI-defined FIFO until up to six clock cycles after you write the data to the FIFO. Use the Timed Out? output of the FIFO Method Node configured with the Read or Write method to determine when the data is ready.

[anurocks]

Hi Adnan

Thanks for the quick reply.

Actually i am trying to program spi eeprom using spi_dual_port_example.But this example is not working properly for my eeprom.

my real time VIs are working fine(i am able to write correct data on fpga registers) but  fpga vi is giving random values while reading from eeprom.But sometimes it reads correctly too.

Also in this example 2 read and 2 write FIFOs are used.Out of which 1 set is VI defined FIFO which is Flip Flop n the other set is fpga FIFO which is block type.So i am worried whether this is memory issue.

I am not able to point out where is the exact problem.Please help to solve this issue

Thanks

Anurag