cRIO Control Program Help

[Jlerma94]

Hello everyone,

I'll start by apologizing if I miss any etiquette for posting a help request on the forums. I'm still relatively new to labview and completely new to the forum.

I've been tasked with creating a program for my work that is supposed to control a testing fixture. The fixture involves 3 string pots which track the three different control positions. The controls are moved by a motor that is reversed using a relay (2 inputs per motor, one controls direction one turns it on). The program should also control when the main motor for the fixture is running with a simple on. The program is supposed to go through three stages, toggled at specific times. I'm using an analog card to track the pot control positions, and a digital card to control the motors. The idea was to have to excitation voltage toggle the relays and motors as needed.

Labview hardware that I have for the current setup is as follows:

cRIO-9082

Analog card NI 9205

Digital card NI 9403

I also do not have access to real time on the cRIO. I am restricted to using the windows environment on the cRIO and have to build applications as the cRIO doesn't have an active version of labview on it.

I've attached what I have so far to this post in hopes that someone can understand what's going on and could give me some pointers on the current issue, and anything that I've done wrong/could do better. The contents of the zip is the project, main VI, FPGA VI, the created sub VIs, and an excel file showing the pin layout.

So far I haven't been able to actually test if what I've done is correct due to getting the memory is full error. That's probably the first thing I need to get through. If someone needs more information please ask, like I said I'm pretty new at this and don't have a mentor at my work for this.

[GerdW]

Hi Jlerma,

you really should do some training courses before starting to code for RT and FPGA. Reallly…

• Your FPGA cannot access any global variables of your "my computer" VI.
• That "New Fixture Control" should run on the cRIO - and so it should be placed in the cRIO part of your project tree.
• Organize all those bits in those globals into (typedefined) clusters…
• Why do you start the FPGA with each iteration of your Main VI loop - and close AND reset it also with each iteration??? (I don't think this will work…)

General suggestion:

Take the training resources offered in the header of this LabVIEW board.

Also take the training resources for RT programming.

Then tackle the training for FPGA.

Examine the example VIs coming with LabVIEW.

Then explore the example projects coming with LabVIEW. There are examples including RT and FPGA targets explaining how to transfer data between the parts of such projects!

It's a steep learning curve - and you need to take it!

[Jlerma94]

Thank you for the response GerdW,

I'm becoming more aware of this, and will likely be dedicating my personal time to doing the labVIEW training.

From your feedback I took another attempt at the program. It no longer stops from a memory issue, and will run the time loop just fine. Now it just seems like the FPGA VI doesn't get transferred when I build an application for the cRIO. I'm assuming this has to do with the comment that you made about the host VI running on the cRIO. I've tried moving it to the cRIO, but I'm met with the plethora of errors saying that most of the items in the host VI are not compatible with the FPGA setup. I'm sure I'm missing something here.

I've attached the current version of the program and the VIs in a zip with this post.

Thank you again for the help, and I apologize if this is made more painful because of the fact that I'm so unfamiliar with the system and software I'm working with.

[GerdW]

Hi Jlerma,

Now it just seems like the FPGA VI doesn't get transferred when I build an application for the cRIO.

Well again: do the RIO and FPGA related training. Examine the example projects coming with LaVIEW…

I've tried moving it to the cRIO, but I'm met with the plethora of errors saying that most of the items in the host VI are not compatible with the FPGA setup. I'm sure I'm missing something here.

The RT and FPGA targets have their limitations. One side effect is the "not supporting" behaviour for some functions, which run flawless on (Windows) computers. It's explained in the training…