cRIO-9057 FPGA DSP48 usage too high - optimization?

[ilh262]

Hi all, 

I am attempting to program a multi-system controller on the FPGA of a cRIO-9057, which only has 240 DSP48 cells. I am over capacity and am wondering if there is a way to determine what part of my program is taking up so much area, and how to reduce the number of DSP48 cells being used by this program.

Because the project is relatively large, I have attached some snippets from the block diagrams that give insight into the math processes. If anybody has tips for reducing the DSP48 usage, please let me know! 

Thanks in advance.

[ZYOng]

Try How Can I Optimize FPGA Resource Usage or Speed? and Optimizing FPGA Compilation for Area or Speed

[joshdoe420]

Judging from the images you posted, most likely none of them uses DSP48 module.

Do you use any IRR or FIR filter in your project? Because those usually consume a lot of DSP48 resource.

Also unless the requirements call for it, I would recommend using a lower resolution for your fixed-point data type, which could improve the timing requirements.

[Terry_ALE]

Can you post compile results?

What's your sample rate?

If the sample rate is lower than the clock rate of the FPGA, you could  over clock. This allows for using less DSPs.

[ilh262]

Thank you greatly for these resources. I did happen upon the "optimize for area" functionality when I was checking for solutions before this post, but I am not sure that it helped. I believe this is because DSP48 usage reduction, from my understanding, is limited by user programming... Thanks again!

[ilh262]

Thank you, joshdoe420. I do not use FIR/IRR filtering, but the controller does require certain discrete values to be stored for one loop iteration.. unfortunately there is nothing to be minimized further here.

And in this instance, the requirement does unfortunately call for higher resolution FXP values, but I will revisit these to make sure values have been set efficiently. Thank you for your advice.

[ilh262]

Terry, please see my compile results below.

When you ask for the sample rate, do you mean the rate I am trying to achieve? Because I cannot successfully compile, I am unsure how to check the rate. Thanks!

[joshdoe420]

How about PID controls, or any kind of signal processing (FFT, beamforming ect.)?

Do you use any IP blocks related to them?

[Terry_ALE]

What is the rate of the AI and/or AO?  That is the sample rate.

The FPGA clock may be say 40 MHz.  These two rates may not be the same.

[Terry_ALE]

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@ilh262 wrote:

Terry, please see my compile results below.

When you ask for the sample rate, do you mean the rate I am trying to achieve? Because I cannot successfully compile, I am unsure how to check the rate. Thanks!

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Can you share more of your code?  Or some kind of diagrams that show the data flow.  How many multiplication functions are you using?  Does it match up to the 320 (give or take) in the compile results?

Are you using any Single Cycle Timed Loops (SCTLs)?  If so, what is their rate?