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best practice for reusable FPGA Interface code

I'm looking for suggestions for best practices when dealing with FPGA interface code. I spent some time making a set of serial interface vi's for some of our sensors working through a 9870 module on a crio. I used the reference example here as the basis of the FPGA code. They work fine as long as the FPGA code doesn't change, but in a real application, there is other code on the FPGA, and the FPGA reference changes. This forces me to update the FPGA reference in all my "reusable" code for each application. I noticed that there is an "up cast" operator, but I don't think this would help me. Either it does exactly what I want (but not for FPGA code that uses a DMA), or it does something else entirelly.


Idealy, I would be able to cast a application specific FPGA reference to a generic FPGA reference that just provides enough information for the reuse code, but doesn't care about other code on the FPGA. Then I wouldn't have to change all my common code for each application.


Is this an accurate assessement of the state of things, or am I missing a better approach?



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Message 1 of 7

One method you might consider is to make a top level FPGA wrapper, then implement your custom code as sub FPGA VIs. You can then use the same FPGA reference for everything, and handle and changes in datatype in the FPGA top level VI.



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Message 2 of 7

Interesting idea. I may have to think about this some more. It seems like the FPGA Wrapper VI would be unnecessary, as long as all FPGA VI's use the same FPGA Reference Type Def with Open FPGA VI Reference. Then I could manage the Type Def on a project basis. It would still force a recompile of all the FPGA interface code when the Type Def gets reassigned in a project, but at least I wouldn't have to manually modify any code.


I'm not sure if I really got your idea because I don't see how the FPGA VI and sub FPGA VIs play. If I make everying a subVI in the FPGA VI, I no longer have access to the subVI's front panel terminals (unless I place them in the wrapper, and that would seem to defeat the purpose).



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Message 3 of 7
You will have access to the front panel controls and indicators of the Sub VI as long as you configure the Connector
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Message 4 of 7
If you happen to be savy with C, there is a new C interface to LabVIEW FPGA that can more dynamically access various bitfiles like you want. But it requires some C expertise. Disregard this otherwise 🙂
Jarrod S.
National Instruments
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Message 5 of 7

Hueter, I'm not sure I'm following you. Maybe you could post an example. I don't see how to get access to the front panel controls of an FPGA subvi from the host vi--even wihen configured through the connector pane--without creating complimentary controls/indicators on the main FPGA VI block diagram (which seems to defeat the purpose of the exercise). It seemed like an intriguing idea, but it doesn't seem possible to configure a reference to a fpga subvi while the main fpga vi is running (only one reference to an FPGA is allowed, at least on crios).


Jarrod, I am not talking about accessing various bitfiles (only one can run at a time, right?). I am talking about creating standard FPGA interface code that can be used on multiple projects without having to reconstruct the VIs based on changes to the FPGA Reference. For example, I have interface code that is used to talk to various sensors through the c-series serial module. Those interface VIs depend on a specific FPGA reference to work. When I create a new project for a crio that has other modules besides the 9870, I will inevitably have a new FPGA VI. There is a subset of the new FPGA VI that is identical to the purely serial one (1 loop/state machine), but other code will be added to handle the other modules. Now the FPGA reference is different, and all my interface VIs are broken when I try to use the new FPGA reference. I have to change the FPGA reference in my interface VIs and then go through an reselect all the IO manually. It's not conducive to reuseable code.


I guess one possibility is to create one Main FPGA VI that has all the IO I could ever need, and then just use whatever subvi's I want in it. I believe this is essentially what's happening in the scan engine. A microcontroller is created on the FPGA with standard IO, and everything is accessed through the abstracted IO.



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Message 6 of 7

You captured what I was going for with the sub VI method in this sentance.


"I guess one possibility is to create one Main FPGA VI that has all the IO I could ever need, and then just use whatever subvi's"


and yes you can only run one bit file at a time. You can programmaticly switch between two bitfiles durring execution, but remeber an one of these FPGA targets only have and 100k burns before it's done, so if you are switching too quickly you will drammaticly reduce the FPGA lifespan.

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Message 7 of 7