Xilinx Compilation Error: HDLCompiler:432 Formal <eiosignal> has no actual or default value

[DiracDeltaForce]

Hi,

I have compiled several programs for sbRIOs previously but have not run into compilation errors before. I can't seem to find any support to see what is actually going poorly. Any help with this would be appreciated!

The Compilation Status summary is as follows: 

LabVIEW FPGA: The compilation failed due to a xilinx error.

Details:
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 87: Formal <eiosignal> has no actual or default value.
INFO:TclTasksC:1850 - process run : Synthesize - XST is done.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000032_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 106: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000033_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 125: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000034_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 144: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000035_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 163: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000036_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 182: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000037_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 201: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000038_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 220: Formal <eiosignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000039_CustomNode.vhd" Line 18. eiosignal is declared here
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd" Line 50: Unit <vhdl_labview> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\R6n310u_Z1R8lYC\NiFpgaAG_00000031_SequenceFrame.vhd ignored due to errors

-->

Total memory usage is 189944 kilobytes

Number of errors : 9 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Process "Synthesize - XST" failed

[Puchkov]

That problem is described in the following whitepaper (most likely will resolve this error):

Why do I receive ERROR:HDLCompiler:432 when compiling the NI 5781 CLIP in LabVIEW 2011?

http://digital.ni.com/public.nsf/allkb/DDA7A5F9C331D23A862578F8004F7705

[DiracDeltaForce]

Hi Puchov,

Thanks for the assistance. I tried to install the posted solution, but was not able to. I instead received a notice that I already had a newer version installed. Is there a way to see which version is currently installed? And might you have another possible solution since the last one didn't work. Again, thank you so much for the help.

-Zach

[Puchkov]

Which versions of the following software do you have installed?

1. LabVIEW
2. LabVIEW FPGA
3. NI-RIO
4. Xilinx Compilation Tool

Assuming all of the version are compatible with each other (hopefully the latest versions), then might recommend to compile using another workstation and see if you get the same compilation error. This error happens with every project or just one? In worst case scenario, a reinstallation might be required.

[DiracDeltaForce]

Hi Puchkov

I'm using:

LabVIEW 2013 f2 13.0.0

FPGA 13.0.0

NI-RIO 13.1.1

Xilinx Compiliation Tool 14.4

I did as you suggested and tried compiling other projects, an old one for another version of sbRIO, and a simple test project for the current sbRIO we're using. Both seemed to compile fine. I don't have access to another workstation right now, but I'll try to send the project over to someone else who does. Thanks for the help so far!

[Spex]

Hi DiracDeltaForce,

Which Single-Board RIO target are you using?

Are you using any custom HDL or CLIP nodes in your LabVIEW FPGA diagram?

The error seems to indicate it is associated with a Sequence Structure, and potentially Elemental IO (eio).  Are you using FPGA IO nodes within a sequence structure in your code?  Based on the text of the error, these are the places in your code I would attempt to isolate and determine the source of the error.

Regards,

[DiracDeltaForce]

Hi Spex,

I am trying to interface with an sbRIO 9626. I do have several places within the code where I either read or write to the digital IO within a sequence structure.

I'm not using any HDL or CLIP nodes within my code.

I'll see what I can do about that, but as timing of these read/write events is very important, removing such structures may not be a trival task. Thanks for the help.

DiracDeltaForce

[Spex]

Hi DiracDeltaForce,

As a first pass, I would recommend disabling or deleting a section of code that you suspect may cause the compile error and see if you can get through synthesis.  Once you get through a compile, you have at least isolated the trouble spot.

Something I would look for in your code is attempts to access the same IO node in multiple clock domains, ie inside and outside of SCTL (single-cycle timed loops), timed sequence structures, or in muliple timed structures with different clock rates.  Attempting this would force LabVIEW to create arbitraion and hand-shaking logic to safely pass data between clock domains.  This type of logic doesn't work in a timed structure because the hand-shaking operation takes multiple clock cycles.

If you are only using traditional sequence structures (rather than the timed sequence structures) I wouldn't suspect this type of issue.

-spex

[Intaris · Accepted solution]

I have had similar errors (no actual or default value) when compiling using code which LV would not remove but the Xilinx compiler would due to determining it was unused.  This would generally be unreachable code with a Register read int he main loop, but the Register Write being in a case structure which would not be executed.  Differences int he ability of the LV compiler or the Xilinx compiler to decide what's safe to remove could lead to this.

Other times we have had errors when a clock was specified in the constraints file but the clock was not being used.

Perhaps either of these two seemingly unrelated points might help.

Shane.

[DiracDeltaForce]

Thank you both for the reply. I'll investigate my code a bit further and come back with an update.