From Friday, April 19th (11:00 PM CDT) through Saturday, April 20th (2:00 PM CDT), 2024, ni.com will undergo system upgrades that may result in temporary service interruption.

We appreciate your patience as we improve our online experience.

Home Community Discussion Forums Most Active Software Boards LabVIEW Topic

LabVIEW

cancel
Turn on suggestions
Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.
Showing results for 
Search instead for 
Did you mean: 

Xilinx Compilation Error: HDLCompiler:432 Formal <eiosignal> has no actual or default value

Solved!
Go to solution

Re: Xilinx Compilation Error: HDLCompiler:432 Formal <eiosignal> has no actual or default value

‎08-19-2014 07:08 PM

Hello everyone,

 

I've gone through the code and found a section that had a disable structure around a section of the code that would enable or disable the output setting of the DIO ports. I deleted these sections (they were there from an early version), and the FPGA program compiled like a charm. Thank you all for your help and insight. 

 

DiracDeltaForce

0 Kudos
Message 11 of 11
(485 Views)
Reply