Xilinx Block Ram with VHDL

[awang_synovus]

I am currently trying to interact with the Block RAM in Xilinx Spartan 6 FPGA. In the IP Integration Node, I have a large chunk of VHDL codes that need to access to the Block RAM. I understand there is a Xilinx Core Generator so I can create a BRAM in Block Digram; However, I would like  to access to the BRAM in the VHDL code. Have anyone tried to access to Xilinx BRAM with VHDL before? 

[Dragis]

Are you wanting to access the Block RAM from both the G diagram and within the VHDL? It would be helpful to have a high-level picture of what needs to communicate with the RAM.

[awang_synovus]

Thank you for yoru reply. 

Not Both. I just want to access within the VHDL code. So currently, I have a large chunk of VHDL code which the BRAM acess is not programmed. I would like to finish the VHDL code so that the VHDL code is fully programmed with access to BRAM, and I can call this VHDL code with IP node in LabVIEW.

[Dragis]

In that case using the Block Memory Generator is fine. When you import the VHDL into an IPIN node in LabVIEW FPGA make sure to include those generated files in the IPIN configuration. 

As far as using the block memory in VHDL, the Block Memory Generator will generate a template I believe which shows how to hook it up. If not there are numerous resources online with how to instantiate VHDL entities and call them. 

[awang_synovus]

Ya I have tried these generated files but it didnt work. Do you have any resources that I can refer to?

[awang_synovus]

Anyone has experiences with this?

[T-REX$]

Well, I don't have experience with this specifically, but I do have a recomendation:

Get your VHDL working in ISE/whatever IDE you use, build it into an NGC, and call that via the IPIN/CLIP Node. I've found this generally easier than trying to reference a bunch of support files in the nodes. If you're using CLIP, I believe you'll have to create a VHDL wrapper that calls into the NGC, and include the NGC as a support file.

Also, in your build settings in ISE, you'll need to uncheck "Add IO Buffers" and set "Pack IO registers into IOBs" to no.

Hopefully that lets you work around any file dependency issues.

[Dragis]

You might also try the built in Xilinx blocks that are configurable from within LabVIEW FPGA. There is a palette specifically dedicated to Xilinx core generator blocks. https://www.ni.com/en/shop/electronic-test-instrumentation/add-ons-for-electronic-test-and-instrumen...