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While loop with unwired stop button in FPGA?

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I have seen FPGA examples with a while loop where nothing is wired to the stop button. On a PC target this would throw an error. What does it mean?

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Accepted by ToeCutter

I think you are talking about "Timed Loops" which are "Single Cycle Timed Loops" on FPGA.

 

As FPGA is meant to run as long as it is powered, a software "Stop" doesnt make much sense.

 

Norbert

Norbert
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You are correct, Norbert, it is a timed loop. I am used to seeing single cycle timed loops with a 'TRUE' constant wired to the stop. Guess it is not necessary.

 

Thanks

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