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Watchdog Timer In Hybrid Mode

Hi, 

 

I'm going to be using a cRIO 9030 in hybrid mode with a NI9381 as my FPGA module. I'm using a couple of example templates to feel out the FPGA programming and I have a question regarding the watchdog timers. Would I utilize the RT Watchdog in hybrid mode or would I utilize the FPGA watchdog timer for my project? Or would it be a combination of the two, given I'm only using one of my modules as an FPGA program. Is it possible to use the RT watchdog along with an FPGA watchdog? 

 

I'm referencing the following example projects; LabVIEW FPGA Waveform Acquisition and Logging on CompactRIO and LabVIEW FPGA Control on Compact RIO. 

 

Looking at the code it would seem that the Waveform Acquisition is using the RT Watchdog while the FPGA control is using the FPGA Control watchdog. My guess is that the waveform is using the RT watchdog because it's only acquiring data and there isn't any mission critical outputs on the FPGA side that will cause a critical error from occurring. Whereas the FPGA control template is using the FPGA watchdog because is uses a control loop and must be put into a safe state in the event the watchdog times out. 

 

If this seems like a fair estimation as to the breakdown of the watchdog timers, I feel my application will be okay with the RT watchdog as I'm using the module to acquire data and will not use the FPGA program with any mission critical control loops or outputs that would need to be put into a safe state. 

 

 

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Hi T._P_Tithering…,

 

You are right with your thoughts, the only situations where we want to use a watchdog in the FPGA is when there is something critical being managed by it, otherwise, we want to save as many resources as possible from the FPGA.

 

Check this link, it refers to watchdog in RT http://zone.ni.com/reference/en-XX/help/370622N-01/lvrtvihelp/pxi_watchdog_vis/

 

 

In case you want to check FPGA status, you can also use heartbeats that is a similar approach http://forums.ni.com/t5/Example-Program-Drafts/FPGA-Heartbeat-Methods/ta-p/3520672

 

Regards,

PedroR

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Hi Pedro, 

 

Thanks for the feedback. I'll be sure to implement the FPGA status because I think it'll be good practice. 

 

Thanks again!

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T._P_Tithering…, it's a pleasure. Good luck with your application.

 

Regards,

PedroR

 

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