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VHDL Code protection in release mode

I am  facing an issue regarding integration of VHDL codes in LabVIEW environment. As we can protect/lock LabVIEW VIs in release mode with password protection. Every VI may be protected in this way and can't be seen by the user. The problem arises when we integrated VHDL codes within our project. I am not been able to lock them,  till now, because in release mode, users can easily open the imported HDL files. And can't release VI in this way. Is there any method that VHDL codes that are included in the design are also locked in release mode, so that no user is reading the propriety codes? 

Cheers

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Any protection that would do this will be weak. If the compiler can read the code, it's just security by obfuscation. Meaning, it will only stop interested people for a little while... Once the encryption method is known, reversing is a peace of cake.

 

This is indeed how LabVIEW locks the diagrams...

 

Anyway, I don't think there are ways to do even this weak protection (but I'm no VHDL expert)... 

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@wiebe@CARYA  is there any encryption method at all? If you know any then please guide.

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@303032 wrote:

@wiebe@CARYA  is there any encryption method at all? If you know any then please guide.


For VIs? No, not really.

 

The PW protection is comparable in functionality with a lock on a door. If someone wants to get it, he can pick the lock. The lock is there so people know it's protected, and potentially illegal to go proceed.

 

If you want to be sure VI code can't be read, you'll need to remove diagrams. But then LabVIEW can't read the diagrams either anymore. So the code can't be recompiled... You'll get the same effect by making an exe or dll containing the IP. I don't think this will work for FPGA code, as each compile would need the diagram to be available.

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There are encryption methods used by Xilinx.  When doing a LV FPGA compile, the files stored locally on your computer are encrypted, yet the Xilinx compiler seems to be able to use them.

 

You might be better off going to a Xilinx source to find this out. Possible showstopper is if the encrypted VHDL files can no longer be linked to via LabVIEW.  Then you'll have protected them so well, even you can't use them any more...... Smiley LOL

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@Intaris wrote:

There are encryption methods used by Xilinx.  When doing a LV FPGA compile, the files stored locally on your computer are encrypted, yet the Xilinx compiler seems to be able to use them.


AFAIK, that encryption is custom for NI. And, OT, probably also the reason the compiler lagging behind on updates. As mentioned, if the compiler can decrypt it, it's also decryptable by everyone else.

 

The moment NI releases how to encrypt it, you (and everyone else) will know how to decrypt it. So I doubt they will tell you.

 

Security through obscurity. If that false feeling of protection works for you...

 

Of course, if you only have 10 customers, it will work by security through minority. But that doesn't make it safe.

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The feature to encrypt VHDL for the Xilinx toolchain is a feature of the Xilinx toolchain and requires a license from Xilinx to use it. I not exactly sure how this is impelemented but I would guess that they use private and public key encryption for this.When you purchase a license, you receive probably a encryption key that is generated using a personalized public key and the Xilinx tool then recognizes the fact that the vhdl (or even bistream) is encrypted and decrypts it in memory to process using the Xilinx private key. While not totally foolproof, since there would be somehow the private key embedded in the toolchain, it is a lot more than just security through obscurity. But they may use an even more advanced scheme than this especially if the tools can depend on online communication so the private key would never even need to leave the Xilinx servers at all.

 

https://www.xilinx.com/products/intellectual-property/ip-encryption.html

Rolf Kalbermatter
My Blog
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