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Hi to all,
I'm trying to use the Configure Component-Level IP wizard to create the declaration XML file automatically from the vhdl.
I'm following the procedure on http://zone.ni.com/reference/en-XX/help/371599N-01/lvfpgahelp/fpga_clip_clock_ex_code/
when I try to do "check syntax" in step 3 of 9 I always get the following error:
Compiling architecture rtl of entity xil_defaultlib.clipgenerateclks [clipgenerateclks]
gcc.exe: Internal error: Aborted (program collect2)
Please submit a full bug report.
See <URL:http://www.mingw.org/bugs.shtml> for instructions.
Fix the above error and check syntax again.
Can someone help me?
Thanks in advance.
Giovanni Maio
You have to update mingw to newer version, read this topic: https://forums.ni.com/t5/LabVIEW/Component-Level-IP-Generate-and-Check-Syntax-Error/td-p/3355591
Hi,
Thanks for the reply.
I followed the steps recommended by you, but now I get the following new error:
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/ClipGenerateClks/obj/xsim_0.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
Fix the above error and check syntax again.
do you have any idea?
Thanks in advance.
Giovanni
A quick look at Xilinx forums shows two ways to fix this:
1. Upgrade Vivado tools to newer version (by the way, what LV FPGA / Vivado tools are you using? And what operating system?). That would mean upgrading LabVIEW. Also - check the links in this thread for more information about Vivado/Windows compatibility: https://forums.ni.com/t5/LabVIEW/LabVIEW-2015-Windows-10-Configure-Xilinx-IP-not-working/m-p/3668520...
2. Finding the source of the problem and fixing it, as described here: https://forums.xilinx.com/t5/Simulation-and-Verification/One-solution-to-error-quot-Failed-to-compil... or here: https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-2017-2-Simulation-XSIM-43-3409-Faile... (note that both topics describe how to do it on Linux, so you have to port them to Windows if that's your case).
Good morning,
The software configuration of my system is as follows:
- Windows Server 2012 R2, but I run Labview in compatibility mode (Windows 😎
- NI Labview 15.0.0 (32 bit)
- Vivado 2014.4
- Xilinx 14.7
- gcc version 8.1.0 (i686-posix-dwarf-rev0, Built by MinGW-W64 project)
1. Compatibility is there;
2. In my system, "libtinfo" is not present.
Thanks
Giovanni