VHDL 2008 with LabVIEW FPGA CLIP

[rkmadse]

I am attempting to save myself and my company a lot of time by using some already built IP within LabVIEW FPGA.

The code is written in VHDL 2008.

Do any LabVIEW FPGA versions with the Xilinx toolkit support VHDL 2008?

I haven't been able to find a good document that explains what is supported where.

Thanks,

Kellen

[Terry_ALE]

I assume you have reviewed https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000x0jiCAA&l=en-US

From my experiences VHDL 2008 should work but I agree that NI should provide us with more documentation for this topic.

[dklipec · Accepted solution]

All shipping versions of LabVIEW ship with 2008 compliant compilers.  The version of Vivado is documented here https://www.ni.com/en/support/documentation/compatibility/19/compatibility-between-xilinx-compilatio...

However, because of the way the compilation is invoked, you will not be able to put vhdl-2008 compliant files in the compile without netlisting them, and using a VHDL93-style wrapper for the netlist.

I've attached a series of files to demonstrate how to do this.  You can use both the CLIP Wizard and IP Integration Node to pull this in.  Both will work, although the IP Integration Node flow will be easier to simulate to note that you did it correctly.

We start with 'top.vhd' which is what we'll use as the top-level VHDL file when we make the netlist.  This contains the simplest new feature of VHDL-2008, implicit conversion of std_logic to boolean in operators.

You'll compile top.vhd into top.edn using the script netgen.tcl, which you'd invoke as

c:\NiFpga\programs\Vivado2015_4\bin\vivado -mode batch -source netgen.tcl

The actual path may vary on your system depending on version of Vivado you are using.

This gets instanced in wrapper.vhd (which, as I'll discuss later, is an awful name to use).  Then we then drop an IP Integration Node, add wrapper.vhd and top.edn as source files, set the wrapper as the top-level for the import, and set the simulation model to post-synthesis on the top.edn.  Step through the dialogs as appropriate.

Gotchas

1. When you netlist the VHDL, you are choosing a part.  If your code uses primitives or other IP, you may run into issues when using that netlist on another part.  In some cases, Vivado can retarget these primitives and everything works.  Others it can't.
2. When you generate the simulation model in LabVIEW, you may run into 1.  The only way to avoid this would be to not make your block simulation friendly (ie: a false simulation model)
3. LV always uses a Kintex-7 part to generate Vivado simulation models.  This can be the source of problems with 2.
4. Filenames.  LabVIEW does not have a magic way to resolve the fact that filenames have to be unique in a VHDL compilation.  If you want to incorporate large amounts of VHDL, it is easy to get into a bad habit of poorly naming your wrappers or duplicating files around.  Remember that LabVIEW is going to pool all those together for one build, and so you need to come up with a unique way to name all files that will end up in the compilation.  If you want to reuse the same VHDL file in multiple IP Integration Nodes, it has to be the exact same file on disk (not one identically named).
5. Current LabVIEW versions encrypt all VHDL sent to the compilation.  Encrypted files don't generate user-visible errors.  If you wish to suppress this, you need to rename the files with the prefix UserRTL_

[rkmadse]

So one thing I have run into and am having problems with is taking a VHDL file that has signals designated as "inout". If I successfully create a netlist with the file that has the inout, and then create a wrapper it seems like the wrapper will also have the "inout". So in this case I need to edit the IP to split those "inout" signals into separate signals so that the wrapper can still be 93 compliant. 

Any thoughts or does this sound correct to you? 

--Kellen