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Survey: How do you run LabVIEW FPGA VIs?

Hello,

 

Our LabVIEW NXG FPGA team is investigating how users run FPGA VIs.  We've create a short survey aimed at people who create FPGA VIs in LabVIEW (not NXG), but all individuals are welcome to participate. This survey should take no more than 5 minutes to complete and your responses will be an important consideration in our design process. 

 

https://www.surveygizmo.com/s3/4434527/FPGA-Hardware-Survey

 

Please complete the survey by 5:00pm (CST) on Tuesday, July 3rd. 

 

Thanks,

Salvador Santolucito

Product Owner

National Instruments

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run or deploy? Seems the safest way, if you set it to run on startup. Then when cRIO boots, first the FPGA starts. That finds all modules. Then you can access them via VISA plus see them in MAX. I had trouble with the FPGA not starting before anything else started

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When you get into the survey they make it plain they are talking about debug techniques.

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I get where this survey is getting at, and as soon as I saw the title I knew, because this is a major limitation I was told that NXG has on FPGA development at the moment.

 

In current LabVIEW when I'm debugging a VI I'm running that VI.  It compiles, downloads and now I can interact with the front panel controls testing the interface.  I often add controls that simulate other things happening to test parts of the FPGA.  I'm only every building the VI into a bit file once I am confident in the FPGA code.  I haven't done much FPGA development recently but I wonder how the newer simulation features would help me debug my code before having to deploy.  Still I think people associate LabVIEW with this rapid prototyping development where I make a change, hit run, and see the results.  Sure FPGA has a bit of a delay there with compiling, but my point is this is a workflow developers in G are used to.

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I second Hoovahh on this one.  Interactive debugging has become an integral part of my FPGA testing.  The only way I could do without it would be to autogenerate a VI which simulates the actual FP of the FPGA VI but operates via FPGA bitfile reference.  If I understand correctly, this is kind of what Interactive mode does anyway.

 

One thing I'd actually like to see solved is the inability to run code in interactive mode if a single change in the VI hierarchy is registered.  Sometimes I just want to test snapshots of ongoing code development to double-check that I haven't broken anything.  Having to stop changing code for 2 hours is a major workflow killer.

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