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Strange behaviour of DIO pins of sbRIO

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Hello,

 

I use an SHT7X temperature/humidity sensor which gives digital output. The sensor has two digital lines, clock line and data line. The data line is bi-directional. A pull up resistor of 10k ohms across the data pin is used to drive the data high (voltage level =3.3v). The sensor works on an I2C (kind of) protocol.

 

The digital pin (here the data pin) of the sbRIO-9633 drops "low" when a high is sent through the program and remains "high" (due to the pull-up) when a "low" is sent to the pin through the program. What's the explaination? What happens when a pin is already high (due to the pull up) and the user also sends a high to it?

Does it drop to zero? Why?

 

 

Note: In the FPGA program, the data pin is configured accordingly. That is, the output setting (enable and disable) is configured according to its bidirectionality operation.

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Is the 'strange behavior' replicated if you disconnect the sensor (but keep the pull up resistors) and measure the output voltage?

 

In the datasheet for the temp sensor you are using, it mentions that the host controller should only drive the DATA signal low.  The pullup resistor should be the only way to pull the signal high.  You should never write TRUE to the DATA Digital IO node connected to this sensor.

 

When I need to communicate with I2C style logic (drive low, external pull high/tristate), I typically set the output of the DIO lines to FALSE initially, and use the "Set Output Enable" method to toggle between driving low (Output enable = TRUE) and letting the external pull-up resistor pull high (Tristate/Output enable = FALSE).  In this mode, you never have to write a TRUE to the DIO pin and risk contending with the external sensor logic.

 

Can you share a screenshot or example code of a simple area of this code that replicates the 'strange behavior'.

 

An external pull up or pull down resistor should not have an impact on the actual output voltage when being 'driven' by the FPGA, assuming the pull resistor is appropriately sized.  In this case, you should never need to 'drive' the output high.  You should be setting the output to tristate/High-Z when you want a high signal on the DATA line.

 

 

 

 

 

Spex
National Instruments

To the pessimist, the glass is half empty; to the optimist, the glass is half full; to the engineer, the glass is twice as big as it needs to be has a 2x safety factor...
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Hello Spex,

 

Thank you for your reply.

 

I have attached the VI snippet which causes the "strange behavior". This is how I am actually configuring it. Is it the other way round? (Should I swap the "true" and "false" cases of the case structure?)

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Solution
Accepted by topic author kdm7

kdm7,

 

I can't answer with 100% confidence because your code snippet is out of context, but yes, it appears you should swap the cases of the case structure. (The True case should write "F" to Set Output Enable and the Fals case should write "T" to Set Output Enable.)

 

In addition, it probably isn't necessary to repeatedly write "F" to DIO26.  Once you write "F" to DIO26 once, the logic will persist until you write to DIO26 again, regardless of what happens externally on the DIO line and whether the output driver is enabled or disabled.

 

You should also understand that using the FPGA IO node to write "F" to DIO26 both writes "F" and enables the output.  If you want to separate the act of writing the value from enabling the output, then you need to use the "Set Output Data" method to write to the DIO line without impacting the output enable. 

 

If you take the advice in the two paragraphs above, then you can eliminate the case structure completely and just write inverted logic to "Set Output Enable" rather than having the two cases of additional logic.  You would just need to initialize the DIO line Data to False before getting to your logic.

 

This page of the LabVIEW help has the best set of documentation that explains how the FPGA DIO nodes work relative to the "Set Output Enable" and "Set Output Data" methods:

 

Using FPGA I/O (FPGA Module)

Spex
National Instruments

To the pessimist, the glass is half empty; to the optimist, the glass is half full; to the engineer, the glass is twice as big as it needs to be has a 2x safety factor...
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