LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

Starting/ending two digital output signals with finite samples exactly at the same time

Solved!
Go to solution

Hello everybody,

 

my goal is to generate two digital output (DO) signals with finite samples. The thing is that they have to start at the same time and after N-samples they have to end at the same time as well.

The first DO signal is a clock signal. The second DO signal is the digital data signal.

In my application i have a daisy chain of 16 shift registers each storing 8 Bits which requires a total of 16*8=128 Bits digital data output signal. With my DO clock signal i will push the 128 Bits data signal to the shift register chain, one Bit at each rising edge of the clock . The clock has to start and stop exactly at the same time with the digital data signal otherwise data will thrown away from the shift register daisy chain.

 

I used another main clock signal to trigger (with DAQmx Start Trigger Digital Edge) both my clock DO signal and digital data DO signal so they start at the same time but it didn't help. Sometimes the data signal starts before the clock signal or vice versa. How can i ensure that both signals (my digital clock output signal and digital data output signal) start and end fully synchronised which means starting/stopping at the exact same time everytime. What am i doing wrong, how can i change my VI to achieve this goal ?

 

Some details about my VI:

The while-loop on the top gets the data for digital data output signal from the user so it is not relevant for the problem i have. After the user sets the data which is going to be pumped to the shift register daisy chain, the generation of the output signals happens inside a Flat Sequence Structure.

 

I am using:

LabVIEW 17.0.1f3 (64-Bit)

Hardware -> NI PXIe-1073 with NI PXIe-6358

 

Any help is highly appreciated.

Best regards,

Ecafer

Download All
0 Kudos
Message 1 of 11
(1,713 Views)

Hi ecafer,

 


@ecafer wrote:

my goal is to generate two digital output (DO) signals with finite samples. The thing is that they have to start at the same time and after N-samples they have to end at the same time as well.

The first DO signal is a clock signal. The second DO signal is the digital data signal.


Put both channels into just one DAQmx task, so they will start at the same time and also stop at the same time!

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
0 Kudos
Message 2 of 11
(1,707 Views)

Hi GerdW,

thanks for the quick reply.

I tried to implement your suggestion but got an error:

 

Error -200559 occurred at DAQmx Create Channel (DO-Digital Output).vi:6970001

Possible reason(s):

Task cannot contain a channel with the specified channel type, because the task already contains channels with a different channel type.

Create one task for each channel type.

Virtual Channel Name: PXI1Slot2/ctr0
I/O Type Required for Virtual Channel: Counter Output
Physical Channel Name: PXI1Slot2/port0/line5
I/O Type Required for Virtual Channel: Digital Output

Task Name: DO signal generation

 

For channels I used CO Pulse Freq (for the clock signal) and Digital Output (for the digital data signal) since I don't know how to generate a clock signal as a digital output channel, I think this is the reason of the error. How can I create a clock signal as a digital output instead of counter output or how can I implement your suggestion (creating a single task with two channels for both clock and digital data signal) correctly?

 

Best regards,

ecafer

 

 

0 Kudos
Message 3 of 11
(1,667 Views)

Hi ecafer,

 


@ecafer wrote:

For channels I used CO Pulse Freq (for the clock signal) and Digital Output (for the digital data signal) since I don't know how to generate a clock signal as a digital output channel, I think this is the reason of the error. How can I create a clock signal as a digital output instead of counter output or how can I implement your suggestion (creating a single task with two channels for both clock and digital data signal) correctly?


In your first message you just wrote about "DO signals", but not about counters vs. "usual" DO signals…

 

When your DAQ board supports digital waveforms then you can create two waveforms as needed and output them using a DO output task!

(Yes, it does support digital waveforms on port 0!)

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
0 Kudos
Message 4 of 11
(1,657 Views)

Based partly on my understanding (admittedly fuzzy and likely flawed) of your app's requirements and partly on the code you posted, here's some advice:  Start breaking this problem down into smaller pieces before trying to put the pieces back together into a full app.  I don't have time now to go back and forth through all the Q&A it'd take to iron out the details, but I see a lot of things that raise questions.  Brief highlights:

 

1. your front panel suggests 16 digital channels with delays measured in nanosec.  You eventually use that info to make a waveform that you feed to a 1-channel DO task.  I'm surprised there's no Digital Waveform graph to show what this digital waveform looks like.  Have you tested those calcs to confirm that they produce the right digital waveform?

 

2. My best guess is that you're interfacing to some external device that needs 2 digital signals, clock and data.  You probably should want a stable and correct data value when the clock edge occurs rather than have both clock and data transitioning simultaneously.   This would lead to a DO task whose own sample clock is at least 2x the speed of the clock signal you want to generate for the external device.   Then each data value lasts for 2 DO sample intervals, and the external clock signal you generate has its edge right in the middle of that 2-sample time period.

 

3. As @GerdW already said, to do things this way both DO output signals going to the external device need to be in 1 single hardware-clocked DO task.

 

4. With your X-series device, the DO task can derive its own sample clock internally so you don't *have* to use a counter task.

 

5. Go open a digital waveform generation example, save it under a new name, and start experimenting with it.   Turn the data into digital waveforms and graph it on the GUI.  Spend some time getting more grounding in defining and generating multi-line DO waveforms, 

 

 

-Kevin P

CAUTION! New LabVIEW adopters -- it's too late for me, but you *can* save yourself. The new subscription policy for LabVIEW puts NI's hand in your wallet for the rest of your working life. Are you sure you're *that* dedicated to LabVIEW? (Summary of my reasons in this post, part of a voluminous thread of mostly complaints starting here).
0 Kudos
Message 5 of 11
(1,649 Views)

Hi Kevin P,

 


@Kevin_Price wrote:

Have you tested those calcs to confirm that they produce the right digital waveform?


 Yes, i use an oscilloscope to confirm the output signals and my app generates the desired digital data output correctly. It also generates the clock signal as desired. My problem is bringing these two signals in one task so that they start simultaneously (with freq_clk = 2 * freq_data).

 


@Kevin_Price wrote:

2. My best guess is that you're interfacing to some external device that needs 2 digital signals, clock and data.


This is exactly the case. I am interfacing a daisy chain of 16 delay line ICs. They need a common clock signal and the data which is 8 Bits for each IC (16*8 = 128 Bits in total for the whole daisy chain). With every clock pulse, the data is shifted into the chain of delay line ICs.

 

@Kevin_Price wrote:

3. As @GerdW already said, to do things this way both DO output signals going to the external device need to be in 1 single hardware-clocked DO task.

 

4. With your X-series device, the DO task can derive its own sample clock internally so you don't *have* to use a counter task.


As the hardware clock i use the Ctr0InternalOutput. Please check my new VI which is much more clear and managable than the original app.

 

What I am trying to achieve is actually really easy. The following image file (DO_sigs.png) shows my desired digital output signals (clock AND data signal), for the example bit sequence 10010. The upper signal is the data signal and the lower one is the clock signal.

With the VI in the attechment i get a error:

Error -200524 occurred at DO.vi

Possible reason(s):

Write cannot be performed, because the number of channels in the data does not match the number of channels in the task.

When writing, supply data for all channels in the task. Alternatively, modify the task to contain the same number of channels as the data written.

Number of Channels in Task: 2
Number of Channels in Data: 1

Task Name: DigOut

 

I don't understand it because I think that I am supplying both channels in the task (one channel for the clock DO signal and another one for the data Do signal) with data?

How should I change my VI in order to get the desired clock AND data DO signals in output lines ? In the waveform and digital output examples of Labview I couldn't find any case in which multiple digital output signals are generated simultaneosly.

 

Best regards,

Ecafer

 

 

Download All
0 Kudos
Message 6 of 11
(1,595 Views)

Hi Kevin P,

 


@Kevin_Price wrote:

Have you tested those calcs to confirm that they produce the right digital waveform?


 Yes, i use an oscilloscope to confirm the output signals and my app generates the desired digital data output correctly. It also generates the clock signal as desired. My problem is bringing these two signals in one task so that they start simultaneously (with freq_clk = 2 * freq_data).

 


@Kevin_Price wrote:

2. My best guess is that you're interfacing to some external device that needs 2 digital signals, clock and data.


This is exactly the case. I am interfacing a daisy chain of 16 delay line ICs. They need a common clock signal and the data which is 8 Bits for each IC (16*8 = 128 Bits in total for the whole daisy chain). With every clock pulse, the data is shifted into the chain of delay line ICs.

 

@Kevin_Price wrote:

3. As @GerdW already said, to do things this way both DO output signals going to the external device need to be in 1 single hardware-clocked DO task.

 

4. With your X-series device, the DO task can derive its own sample clock internally so you don't *have* to use a counter task.


As the hardware clock i use the Ctr0InternalOutput. Please check my new VI which is much more clear and managable than the original app.

 

What I am trying to achieve is actually really easy. The following image file (DO_sigs.png) shows my desired digital output signals (clock AND data signal), for the example bit sequence 10010. The upper signal is the data signal and the lower one is the clock signal.

With the VI in the attechment i get a error:

Error -200524 occurred at DO.vi

Possible reason(s):

Write cannot be performed, because the number of channels in the data does not match the number of channels in the task.

When writing, supply data for all channels in the task. Alternatively, modify the task to contain the same number of channels as the data written.

Number of Channels in Task: 2
Number of Channels in Data: 1

Task Name: DigOut

 

I don't understand it because I think that I am supplying both channels in the task (one channel for the clock DO signal and another one for the data Do signal) with data?

How should I change my VI in order to get the desired clock AND data DO signals in output lines ? In the waveform and digital output examples of Labview I couldn't find any case in which multiple digital output signals are generated simultaneosly.

 

Best regards,

Ecafer

 

Download All
0 Kudos
Message 7 of 11
(1,591 Views)

...

 

0 Kudos
Message 8 of 11
(1,590 Views)

Hi Jim,

 

apparently you took the job from ecafer with the same hardware setup, even with the same image file…

 

Why don't you also take the suggestion here (point 2) provided to ecafer?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
0 Kudos
Message 9 of 11
(1,579 Views)

Hello GerdW,

 

do you have an idea, what am I doing wrong in the VI here in this reply ?

 

Best regards,

Ecafer

0 Kudos
Message 10 of 11
(1,556 Views)