From Friday, April 19th (11:00 PM CDT) through Saturday, April 20th (2:00 PM CDT), 2024, ni.com will undergo system upgrades that may result in temporary service interruption.

We appreciate your patience as we improve our online experience.

LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

SmartHeap Library error

Solved!
Go to solution

Hello ! 

 

I'm using sbRIO 9627 and I'm facing problem of compilation of my FPGA code (Error:SmartHeap Library) as show in tha attached files.

when this error appears,and I do not any actions, the compilation continues but without progression and it goes for more than 3 hours without any progress.

If I choose an action , an other error appears (Runtime Library) and the compilation will stop in few minutes as shown in the attached files.

I tried to solve the problem and I tried to do this https://bit.ly/2ZIRs3R  ; but the problem persists.

 

Can anyone help me ? I appreciate your help and your effort.

0 Kudos
Message 1 of 7
(2,126 Views)

There's no telling what the problem is without seeing some code. Perhaps 700 is still too much, perhaps you have other FIFOs. That FPGA isn't that big...

0 Kudos
Message 2 of 7
(2,100 Views)

Thank you for your answer  wiebe@CARYA 

 

I tried to change the size of FIFO  (700-500-400-200-100) and it is the same problem.

I'm using only one FIFO .

The code is in attached file.

0 Kudos
Message 3 of 7
(2,085 Views)

What's the data type of the FIFO? There's a coercion dot between the AI and the FIFO, which is probably not desirable. Not too sure if it's avoidable, I have no FPGA at hand right now.

 

It shouldn't fail to compile on that, unless you've make a fixed point float with a ridiculous number of bits.

0 Kudos
Message 4 of 7
(2,068 Views)

I don't know if the red dot is the reason of my problem.

 

Can you check this attached file about the data type of FIFO,please?

0 Kudos
Message 5 of 7
(2,062 Views)
Solution
Accepted by topic author Karim_Eng

Hi Karim,

 

why don't you use an U16 datatype instead of this FXP?

(You don't need to answer such "what datatype?" questions if you would attach your project including the lvproj file!)

 

  • I don't see any FIFO in your FPGA VI.
  • In the "subVI3_analog generation" you are using an array of FXP(±, 64,32). In the "main_FPGA" that array is set to a size of 1000 elements: Are you sure you need an array of 1000 elements of 64bit wide FXP numbers? What datatype does that AO pin expect???
Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
0 Kudos
Message 6 of 7
(2,055 Views)

Hi GerdW 

 

yes I used U16 datatype instead of FXP and it compiled successfully.

thank you all for your help.

0 Kudos
Message 7 of 7
(2,037 Views)