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Pass FPGA control values from Non-FPGA VI

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I am using NI PXIe-1062Q Chasis (connected to a Dell workstation Precision 1700) with the following modules :

1. NI PXIe-8381

2. NI PXI 7851 R

3. NI PXIe-6738

4. NI PXIe-6535

In my workstation, I have plugged in the PCIe-8381 module for connecting NI PXIe-8381 to the computer into a PCI-E Gen 3 x16  slot. Now here are my questions :


Q.1. I am trying to control an FPGA sub VI from a Non-FPGA Top level VI. I have attached the both VIs. In the FPGA VI, I switch ON a TTL signal in one channel of Connector 0 of 7851R. After some wait time, I switch off the TTL signal in the channel. I want to control the wait time from my Top level Non-FPGA VI. When I run the Top level VI it does call the FPGA VI and I see a TTL rising and falling on the oscilloscope. But the time of this TTL is always a default value of 0 μs i.e. I get this same pulse when I run just the FPGA VI itself with a wait time of 0 μs.  Even if I give a wait time of say 2 μin the Top level VI, the output is always corresponding to that of  0 μs. The FPGA VI when run on its own (without being called from Top level VI) produces the desired output say, 2,5, 10 μs etc.
I would like to control this wait time from Top level VI. Please suggest what I should do.
Q.2. After when I will be able to control the wait time from Top level VI, I would also like to control the channel of Connector 0 of 7851R where I output this TTL ON and OFF. Is it even possible? On this page, they say its possible. can someone tell me (with an example Host and Sub VI) how??
Here are the screenshots as well:Top Level Non FPGA ViTop Level Non FPGA Vi




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Q1: The FPGA VI has no loop, so it will run just once and terminate. As the FPGA runs (typically) at 40MHz clock the VI will be terminated within ns. Do you really think you can set a Wait time so fast after starting the FPGA that the FPGA will obey your wishes?


Q2: Why don't you try this? Why don't you access FPGA IO directly? Why do you use references with IO nodes?


I also wonder about your VI names: why do you call the FPGA VI as "subVI"?

I guess it's the MainVI running on your FPGA?

Best regards,

using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
Message 2 of 6

Hi GerdW,

Thanks for your suggestions.

May I request you to upload sample VIs for both your answers? I see I have a lot to learn from you.

I will also try on my own but your help will make things easier for me.


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LabVIEW comes with a lot of example VIs and projects!

Please create/open one of those example projects regarding RT/FPGA to see all those mentioned things…

There are also example projects/VIs for most cRIO modules - you can examine them too!

Best regards,

using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Accepted by topic author RRI_user
Hi GerdW,
I was able to control the FPGA VI without any loop. I have attached both VIs. Please comment on the suitability of this code.
Also, I still don't get how to access FPGA IO directly from Non-FPGA VI. I went through many examples of LabVIEW. I will keep on trying.Top_level_Non_FPGA_VITop_level_Non_FPGA_VIFPGA_SubVIFPGA_SubVI
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Most likely you are running your bitfile on opening the reference.  This means that your code on the FPGA is most likely finished long before you write anything to the FP control.


Add a waiting loop on the FPGA so that you can "trigger" when you want the acquisition to start.  This can be a change in the Timer value (using -1 as a sentinel value) or a boolean, whatever you want.  But you need to force the code you want to execute to receive the data you need to control the timing BEFORE it executes.

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