04-06-2021 09:44 PM
Hello.
I have a phase detector in a phase-locked loop, and I want to track a specific value of the phase that happens to occur on resonance. However, I believe that I would need to unwrap the phase to do this. How can I do this on the myRIO's FPGA target?
So far, I have tried converting the Double data types in the "Unwrap Phase PtByPt VI " to FXP, but it doesn't seem to work. I know how to do it on the RT, but I want to do it directly on the target FPGA.
- Thank you
04-07-2021 08:02 AM
So, besides "it doesn't seem to work", do you have any details on what way it is not working?
Perhaps even post your modified code so that others can see if anything is obviously wrong with it?
04-07-2021 10:08 AM
Is the FPGA "acquiring" the Phase? Since most instruments report their values as integers, you should be able to "unwrap the phase" by simply the Quotient and Remainder function in the FPGA. The Quotient would be whatever (integer) value corresponds to two-pi in your system. You may want to shift the "branch cut" to 180° from the phase you are testing.
Example: you are using an encoder that "counts" up to 2048 (or 0 .. 2047). You want to look for a phase close to 0. If you take the remainder mod 2048, then a phase of 1° will be 6 counts, and -1° will be 2048-6 = 2042 counts, so small numbers will be jumping all over the place. However, if you first add 1024 to the counts, 6 + 1024 = 1030 = 1030 mod 2048, which is very close to -6 + 1024 = 1018 = 1018 mod 2048. You've "moved" the discontinuity in the Mod function out of the "area of interest" for your comparison. Do you get the idea?
Bob Schor
04-14-2021 11:54 AM
Yes, that was a vague statement. The unwrap isn't working since the input=output for my implementation of the unwrap, so it is still wrapped. I will try post the code later today.
Sorry for the delay. I didn't receive an email about these replies.
04-14-2021 11:55 AM
Yes, that was a vague statement. The unwrap isn't working since the input=output for my implementation of the unwrap, so it is still wrapped. I will try post the code later today.
Sorry for the delay. I didn't receive an email about these replies.
04-16-2021 04:18 PM
Here is the modified code, if you're curious. Sorry for the delay. School has kept me busy.
If in the project file and using virtual folders: Go to the target FPGA target, then to the "custom Sub VIs" folder, then to the "alternativesToNI" folder and the "_phaseUnwrap_fxpPtByPt.vi" within to find the alternative vi that I mentioned.
If through the .zip file: Go to ... PhaseLockedLoop_04142021.zip\PhaseLockedLoop_04142021\FPGA_VIs\fpgaSubVIs\_phaseUnwrap_fxpPtByPt.vi
04-16-2021 04:25 PM
Hello. Thank you for your suggestion. I will try implementing this. Sorry for the delay. I didn't receive an email about a response on this thread for some reason.
The phase value from the FPGA is an FXP <+/-, 32, 2> value bounded between 1 and -1 which represent pi and -pi. Considering that this does not "count up to 2048", could you elaborate on how I may implement your suggestion? I am admittedly a bit confused in regards to your suggestion. If my FPGA node output is bounded at 1,-1, then should I use 2pi as the quotient?
Node that I use: https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpga/ht_rect_to_polar/